View CS8420-CS_1369852.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

copyright ? cirrus logic, inc. 2007 (all rights reserved) http://www.cirrus.com digital audio sample rate converter features ? complete iec60958, aes3, s/pdif, eiaj cp1201-compatible transceiver with asynchronous sample rate converter ? flexible 3-wire serial digital i/o ports ? 8-khz to 108-khz sample rate range ? 1:3 and 3:1 maximum input to output sample rate ratio ? 128 db dynamic range ? -117 db thd+n at 1 khz ? excellent performance at almost a 1:1 ratio ? excellent clock jitter rejection ? 24-bit i/o words ? pin and microcontroller read/write access to channel status and user data ? microcontroller and stand-alone modes general description the cs8420 is a stereo digital audio sample rate con- verter (src) with aes3-type and serial digital audio inputs, aes3-type and serial digital audio outputs, and includes comprehensive control ability via a 4-wire mi- crocontroller port. channel status and user data can be assembled in block-sized buffers, making read/modify/write cycles easy. digital audio inputs and outputs may be 24, 20, or 16 bits. the input data can be completely asynchronous to the output data, with the output data being synchronous to an external system clock. the cs8420 is available in a 28-pin soic package in both commercial (-10o to +70o c) and automotive grades (-40o to +85o c). the cdb8420 customer dem- onstration board is also available for device evaluation and implementation suggestions. please refer to ?ordering information? on page 93 for or- dering information. target applications incl ude cd-r, dat, md, dvd and vtr equipment, mixing consoles, digital audio trans- mission equipment, high-quality d/a and a/d converters, effects processors, and computer audio systems. serial audio input clock & data recovery misc. control aes3 s/pdif encoder serial audio output receiver aes3 s/pdif decoder sample rate converter c&ubit data buffer control port & registers output clock generator rxn rxp ilrck isclk sdin olrck osclk sdout txp txn rst omck emph u tcbl sda/ cdout scl/ cclk ad1/ cdin ad0/ cs int va+ agnd filt rerr vd+ dgnd h/s rmck driver april '07 ds245f4 cs8420
2 ds245f4 cs8420 table of contents 1. characteristics and specificat ions .......... ................. ................ ................ ................ ........... 6 specified operating conditions .............................................................................................. 6 absolute maximum ratings ...................................................................................................... .. 6 performance specifications .................................................................................................... 7 digital filter characteristics ................................................................................................ .7 dc electrical specifications .. ................ ................ ................ ................ ................ ................ .. 7 digital input characteristics ................................................................................................. .8 digital interface specifications .............. ................ ................ ................. ................ .............. 8 transmitter characteristics .................................................................................................. 8 switching characteristics ..................................................................................................... .. 8 switching characteristics - serial audio ports .............................................................. 9 switching characteristics - control port - spi? mode ............................................. 10 switching characteristics - control port - i2c? mode ............................................... 11 2. typical connection diagram ................................................................................................. .. 12 3. general description ........................................................................................................ ........... 13 4. data i/o flow and clocking options ..................................................................................... 14 5. sample rate converter (src) ................................................................................................ .. 18 5.1 dither .................................................................................................................... ......................... 18 5.2 src locking, varispe ed and the sample rate ratio register ..................................................... 18 6. three-wire serial audio ports .............................................................................................. .19 7. aes3 transmitter and receiver .............................................................................................. 22 7.1 aes3 receiver ..... ................ ................ ................ ................. ................ ............. .......... .................. 22 7.1.1 pll, jitter attenuation, and varispeed .................................................................................. 22 7.1.2 omck out on rmck ........ ................................................................................................ ... 22 7.1.3 error reporting and hold function ....................................................................................... .22 7.1.4 channel status data hand ling ............................................................................................ .. 23 7.1.5 user data handling ...................................................................................................... ......... 23 7.1.6 non-audio auto de tection ................................................................................................ ..... 24 7.2 aes3 transmitter . ................ ................ ................ ................. ................ ............. ........... ................. 24 7.2.1 transmitted frame and channel status boundary timing ................................................... 24 7.2.2 txn and txp drivers ..................................................................................................... ....... 25 7.3 mono mode operation ....................................................................................................... ............ 25 8. aes3 transmitter and receiver .............................................................................................. 28 8.1 sample rate converter .......................... ........................................................................... ............ 28 8.2 non-src delay ............................................................................................................. ................ 29 9. control port description and timing ................................................................................. 30 9.1 spi mode .................................................................................................................. ..................... 30 9.2 i2c mode .................................................................................................................. ...................... 31 9.3 interrupts ................................................................................................................ ........................ 31 10. control port register bit definitions ............................................................................. 32 10.1 memory address pointer (map) ............................................................................................. ..... 32 10.2 miscellaneous control 1 (01h) ............................................................................................ ......... 34 10.3 miscellaneous control 2 (02h) ............................................................................................ ......... 35 10.4 data flow control (03h) .................................................................................................. ............. 36 10.5 clock source control (04h) ............................................................................................... ........... 37 10.6 serial audio input port data format (05h) ................................................................................ ... 38 10.7 serial audio output port data format (06h) ............................................................................... .39 10.8 interrupt 1 register status (07h) (read only) ............................................................................ .40 10.9 interrupt register 2 status (08h) (read only) ............................................................................ .41 10.10 interrupt 1 register mask (09h) ......................................................................................... ........ 41 10.11 interrupt regi ster 1 mode registers msb & lsb (0ah,0 bh) ..................................................... 41 10.12 interrupt 2 register mask (0ch) ......................................................................................... ........ 42
ds245f4 3 cs8420 10.13 interrupt register 2 mode registers msb & l sb (0dh,0eh) ..................................................... 42 10.14 receiver channel status (0fh) (read only) ............................................................................. 43 10.15 receiver error (1 0h) (read only) ........................................................................................ ...... 44 10.16 receiver error mask (11h) ...................... ......................................................................... .......... 45 10.17 channel status data buffer control (12h) ................................................................................ .45 10.18 user data buffer control (13h) .......................................................................................... ........ 46 10.19 sample rate ratio (1eh) (read only) ..................................................................................... .. 47 10.20 c-bit or u-bit data buffer (20h - 37h) . ................................................................................. ...... 47 10.21 cs8420 i.d. and version register (7fh) (rea d only) ............................................................... 47 11. system and applications issu es .............. ................ ................ ................. ................ ............ 4 8 11.1 reset, power down and star t-up options ................................................................................... 48 11.2 transmitter startup ...................................................................................................... ................ 48 11.3 src invalid state .................................. ...................................................................... ................. 49 11.4 c/u buffer data corrupti on ............................................................................................... ........... 49 11.5 block-mode u-data d-to-e bu ffer transfers ............................................................................... 5 0 11.6 id code and revision code ................................................................................................ ........ 50 11.7 power supply, ground ing, and pcb layout ................................................................................. 5 0 11.8 synchronization of multiple cs8420s ...................................................................................... .... 50 11.9 extended range sample rate conversion ................................................................................. 50 12. software mode - pin description ......................................................................................... 51 13. hardware modes ............................................................................................................ ............. 55 13.1 overall description ....... ............................................................................................... ................. 55 13.1.1 hardware mode definitions .................... .......................................................................... ... 55 13.1.2 serial audio port formats .............................................................................................. ..... 55 13.2 hardware mode 1 descriptio n (default data flow, aes3 input) ................ ................ ............ 56 13.2.1 pin description - ha rdware mode 1 .............................. ...................................................... 57 13.3 hardware mode 2 descript ion .............................................................................................. ....... 59 13.3.1 pin description - ha rdware mode 2 .............................. ...................................................... 61 13.4 hardware mode 3 descript ion .............................................................................................. ....... 63 13.4.1 pin description - ha rdware mode 3 .............................. ...................................................... 65 13.5 hardware mode 4 descript ion .............................................................................................. ....... 67 13.5.1 pin description - ha rdware mode 4 .............................. ...................................................... 69 13.6 hardware mode 5 descript ion .............................................................................................. ....... 71 13.6.1 pin description - ha rdware mode 5 .............................. ...................................................... 72 13.7 hardware mode 6 descript ion .............................................................................................. ....... 74 13.7.1 pin description - ha rdware mode 6 .............................. ...................................................... 76 14. external aes3/spdif/iec60958 transmitte r and receiver components ................ 78 14.1 aes3 transmitter external co mponents ..................................................................................... 78 14.2 aes3 receiver external comp onents ........................................................................................ .79 14.3 isolating transformer requirements ....................................................................................... ..... 80 15. channel status and user data buffer ma nagement .................................................. 81 15.1 aes3 channel status(c) bit management .................................................................................. 81 15.1.1 manually accessing the e buffer ........................................................................................ .82 15.1.2 reserving the first 5 bytes in the e buffer ......................................................................... 83 15.1.3 serial copy management system (scms) ......................................................................... 83 15.1.4 channel status data e buffer access ................................................................................. 83 15.1.5 one-byte mode .......................................................................................................... ......... 84 15.1.6 two-byte mode .......................................................................................................... ......... 84 15.2 aes3 user (u) bit management ............................................................................................. ..... 84 15.2.1 mode 1: transmit all zeros ............................................................................................. .... 84 15.2.2 mode 2: block mode ..................................................................................................... ....... 84 15.2.3 iec60958 recommended u data format for consumer applications ............................... 85 15.2.4 mode (3): reserved ..................................................................................................... ........ 85 15.2.5 mode (4): iec consumer b ............................................................................................... .. 85
4 ds245f4 cs8420 16. pll filter ................................................................................................................ ........................ 87 16.1 general .................................................................................................................. ...................... 87 16.2 external filter components ............................................................................................... .......... 87 16.2.1 general ................................................................................................................ ................ 87 16.2.2 capacitor selection ... ................................................................................................. ......... 88 16.2.3 circuit board layout ................................................................................................... ......... 88 16.3 component value selection ........................ ........................................................................ ........ 88 16.3.1 identifying the part revision .......................................................................................... ...... 88 16.3.2 locking to the rxp/rxn receiver inputs .............. ............................................................. 89 16.3.3 locking to the ilrck input ................................. ............................................................ .... 89 16.3.4 jitter tole rance ....................................................................................................... ............. 90 16.3.5 jitter attenuation .... ................................................................................................. ............ 90 17. parameter definitions ..................................................................................................... ......... 91 18. package dimensions ........................................................................................................ .......... 92 thermal characteristics and specifications . ................ ............. ............. ............. ......... 92 19. ordering information ...................................................................................................... ........ 93 20. revision history .......................................................................................................... ................ 93 list of figures figure 1.audio port master mode timing ........................................................................................ ........... 9 figure 2.audio port slave mode and data input timi ng .......................................................................... ... 9 figure 3.spi mode timing ...................................................................................................... .................. 10 figure 4.i2c mode timing ...................................................................................................... ................... 11 figure 5.recommended connection diagram for softwa re mode ........................................................... 12 figure 6.software mode audio data flow switching options ................................................................... 14 figure 7.cs8420 clock routing ................................................................................................. ............... 14 figure 8.serial audio input, using pll, src enabled ............................................................................ .. 16 figure 9.serial audio input, no pll, src enable d .............................................................................. .... 16 figure 10.aes3 input, src enabled ............................................................................................. ........... 16 figure 11.serial audio input, aes3 input clock source, src enabled ... ............. ............. ............. ......... 16 figure 12.serial audio input, src output clocked by aes3 recovered clock ....................................... 16 figure 13.aes3 input, src to serial audio output, se rial audio input to aes3 out ............................... 16 figure 14.aes3 input to serial au dio output, serial audio input to aes3 out, no src ................ ......... 17 figure 15.aes3 input to serial audio output only .............................................................................. ..... 17 figure 16.input serial port to aes3 transmitter .......... ................ ................ ............. ............. ........... ........ 17 figure 17.serial audio input example formats ..... ............................................................................. ...... 20 figure 18.serial audio output ex ample formats ................................................................................. ..... 21 figure 19.aes3 receiver timing for c & u pin output data ................................................................... 23 figure 20.aes3 transmitter timing fo r c, u and v pin input data .......................................................... 26 figure 21.mono mode op eration compared to normal stereo operation ............................................... 27 figure 22.control port timing in spi mode ....... .............................................................................. ......... 30 figure 23.control port timing in i2c mode ..... ................................................................................ .......... 31 figure 24.hardware mode 1 - default data flow, aes3 input ........ ................ ................ ................ ......... 56 figure 25.hardware mode 2 - default data flow, seri al audio input ....................................................... 59 figure 26.hardware mode 3 - transce ive data flow, with src .............................................................. 63 figure 27.hardware mode 4 - tran sceive data flow, without src ...... ................................................... 67 figure 28.hardware mode 5 - aes3 receiver only . ................ ................ ................ ................ ............... .71 figure 29.hardware mode 6 - aes3 transmitter only ....... ................ ................ ............. ............. ............ 74 figure 30.professional output circuit ......................................................................................... .............. 78 figure 31.consumer output circuit ............................................................................................. ............. 78 figure 32.ttl/cmos output circuit .................. ........................................................................... ............ 79 figure 33.professional input circuit .......................................................................................... ................ 79 figure 34.transformerless professi onal input circuit .......................................................................... ..... 79
ds245f4 5 cs8420 figure 35.consumer input circuit .............................................................................................. ............... 80 figure 36.ttl/cmos input circuit .............................................................................................. .............. 80 figure 37.channel status data buffer structure ................................................................................ ....... 81 figure 38.channel status bl ock handling when fso is not equal to fsi ................................................. 82 figure 39.flowchart for reading th e e buffer .................................................................................. ......... 82 figure 40.flowchart for writing the e buffer .................................................................................. ........... 83 figure 41.pll block diagram ................................................................................................... ................ 87 figure 42.recommended layout example .......................................................................................... ..... 88 figure 43.jitter tolerance template ........................................................................................... .............. 90 figure 44.revision d jitter attenuation ....................................................................................... .............. 90 figure 45.revision d1 jitter attenuation ......... ............................................................................. ............. 90 list of tables table 1. minimizing group delay through multiple cs8420s when lock ing to rxp/rxn ...................... 28 table 2. minimizing group delay through multiple cs8420s when lock ing to ilrck ........................... 28 table 3. non-src delay ........................................................................................................ ................... 29 table 4. summary of all bits in the control register ma p ...................................................................... .. 33 table 5. hardware mode definitions ............................................................................................ ............. 55 table 6. serial audio output formats available in hardware mode ... ...................................................... 55 table 7. serial audio input formats available in hardware mode ............................................................ 55 table 8. hardware mode 1 start-up options ..................................................................................... ....... 56 table 9. hw mode 2a copy/c and orig/u pin function ...................................................................... 60 table 10. hw mode 2 serial audio port format selection ................. ...................................................... 6 0 table 11. hardware mode 2 start-up options .................................................................................... ...... 60 table 12. hardware mode 3 start-up options .................................................................................... ...... 64 table 13. hardware mode 4 start-up options .................................................................................... ...... 68 table 14. hardware mode 5 start-up options .................................................................................... ...... 71 table 15. hw 6 copy/c and orig pin function ................................................................................... .75 table 16. hw 6 serial port form at selection ................................................................................... ........ 75 table 17. second line part marking ............................................................................................ ............. 88 table 18. locking to rxp/rxn - fs = 8 to 96 khz ............................................................................... .... 89 table 19. locking to rxp/rxn - fs = 32 to 96 khz* ............................................................................. ... 89 table 20. locking to the ilrck in put .......................................................................................... ............. 89
6 ds245f4 cs8420 1. characteristics and specifications all min/max characteristics and specif ications are guaranteed over the spec ified operating conditions. typical performance characteristics and specifications are derive d from measurements taken at nominal supply voltages and t a = 25c. specified operating conditions agnd, dgnd = 0 v, all voltages with respect to 0 v. absolute maximum ratings agnd, dgnd = 0 v; all voltages with respect to 0 v. operation beyond these limits may result in permanent dam- age to the device. normal operation is not guaranteed at these extremes. notes: 1. transient currents of up to 100 ma will not cause scr latch-up. parameter symbol min typ max units power supply voltage vd+, va+ 4.75 5.0 5.25 v ambient operating temperature: commercial grade automotive grade t a -10 -40 - - +70 +85 c c parameter symbol min max units power supply voltage vd+, va+ - 6.0 v input current, any pin e xcept supplies, rxp/rxn (note 1) i in -10ma input voltage v in -0.3 (vd+) + 0.3 v ambient operating temperature (power applied) t a -55 125 c storage temperature t stg -65 150 c
ds245f4 7 cs8420 performance specifications digital filter characteristics 2. see ?aes3 transmitter and receiver? on page 28. dc electrical specifications agnd = dgnd = 0 v; all voltages with respect to 0 v. 3. power down mode is defined as rst = lo with all clocks and data lines held static. 4. normal operation is defined as rst = hi. parameter* symbol min typ max units dynamic range 120 128 - db input sample rate (serial input port) fsi 8 - 108 khz output sample rate fso 8 - 108 khz output to input sample rate ratio 0.33 - 3 total harmonic distortion + noise 1 khz, -1 dbfs, 0.33 < fso/fsi < 1.7 1 khz, -1 dbfs, 0.33 < fso/fsi < 3 10 khz, -1 dbfs, 0.33 < fso/fsi < 1.7 10 khz, -1 dbfs, 0.33 < fso/fsi < 3 thd+n - - - - - - - - -117 -112 -110 -107 db db db db peak idle channel noise component - - -140 dbfs resolution 16 - 24 bits gain error -0.12 - 0 db parameter* symbol min typ max units passband upsampling downsampling 0 0 - - 0.4535*fsi 0.4535*fso hz hz passband ripple - - 0.007 db stopband (downsampling) 0.5465*fso - fsi/2 hz stopband attenuation 110 - - db group delay (note 2) t gd - - 1.75 ms group delay variation vs. frequency t gd --0.0 s interchannel phase deviation - - 0.0 parameters symbol min typ max units power down mode (note 3) supply current in power down va+ vd+ - - 20 20 - - a a normal operation (note 4) supply current at 48 khz f so and f si va+ vd+ - - 3.7 66 - - ma ma supply current at 96 khz f so and f si va+ vd+ - - 7.0 125 - - ma ma
8 ds245f4 cs8420 digital input characteristics digital interface specifications agnd = dgnd = 0 v; all voltages with respect to 0 v. transmitter c haracteristics switching characteristics inputs: logic 0 = 0 v, logic 1 = vd+; c l = 20 pf. 5. cycle-to-cycle jitter using 32-96 khz external pll components. 6. pll is bypassed (rxd1:0 bits in the clock source cont rol register set to 10b), clock is input to the rmck pin. parameters symbol min typ max units input leakage current i in -1015 a differential input voltage, rxp to rxn v th 200 - - mvpp parameters symbol min max units high-level output voltage (i oh = -3.2 ma), except txp/txn v oh (vd+) - 1.0 - v low-level output voltage (i oh = 3.2 ma), except txp/txn v ol -0.4v high-level output voltage (i oh = -21 ma), txp, txn (vd+) - 0.7 - v low-level output voltage (i oh = 21 ma), txp, txn - 0.7 v high-level input voltage, except rxp, rxn v ih 2.0 (vd+) + 0.3 v low-level input voltage, except rxp, rxn v il -0.3 0.8 v parameters symbol typ units txp output resistance r txp 25 txn output resistance r txn 25 parameter symbol min typ max units rst pin low pulse width 200 - - s omck frequency for omck = 512 * fso 4.096 - 55.3 mhz omck low and high width for omck = 512 * fso 8.2 - - ns omck frequency for omck = 384 * fso 3.072 - 41.5 mhz omck low and high width for omck = 384 * fso 12.3 - - ns omck frequency for omck = 256 * fso 2.048 - 27.7 mhz omck low and high width for omck = 256 * fso 16.4 - - ns pll clock recovery sample rate range 8.0 - 108.0 khz rmck output jitter (note 5) -200-ps rms rmck output duty cycle 40 50 60 % rmck input frequency (note 6) 2.048 - 27.7 mhz rmck input low and high width (note 6) 16.4 - - ns aes3 transmitter ou tput jitter - - 1 ns
ds245f4 9 cs8420 switching characteristics - serial audio ports inputs: logic 0 = 0 v, logic 1 = vd+; c l = 20 pf. 7. the active edges of isclk and osclk are programmable. 8. when osclk, olrck, isclk, and il rck are derived from omck they are clocked from its rising edge. when these signals are derived from rmck , they are clocked from its falling edge. 9. the polarity of ilrck and olrck is programmable. 10. no more than 128 sclk per frame. 11. this delay is to prevent the previous i/osclk edge from being interpreted as the first one after i/olrck has changed. 12. this setup time ensures that this i/osclk edge is interpreted as the first one after i/olrck has changed. parameter symbol min typ max units osclk active edge to sdout output valid (note 7) t dpd - - 25 ns sdin setup time before isclk active edge (note 7) t ds 20 - - ns sdin hold time after isclk active edge (note 7) t dh 20 - - ns master mode o/rmck to i/osclk active edge delay (note 7, 8) t smd 0 - 16 ns o/rmck to i/olrck delay (note 9) t lmd 0 - 17 ns i/osclk and i/olrck duty cycle - 50 - % slave mode i/osclk period (note 10) t sckw 36 - - ns i/osclk input low width t sckl 14 - - ns i/osclk input high width t sckh 14 - - ns i/osclk active edge to i/olrck edge (note 7, 9, 11) t lrckd 20 - - ns i/olrck edge setup before i/osclk active edge (note 7, 9, 12) t lrcks 20 - - ns t ilrck olrck (input) isclk osclk (input) sdin sdout t lrckd lrcks t sckh t sckw t sckl t dpd dh t ds t t smd t lmd hardware mode software mode isclk osclk (output) ilrck olrck (output) rmck (output) rmck (output) omck (input) figure 1. audio port master mode timing figure 2. audio port slave mode and data input timing
10 ds245f4 cs8420 switching characteristics - control port - spi? mode inputs: logic 0 = 0 v, logic 1 = vd+; c l = 20 pf. 13. if fso or fsi is lower than 46.875 khz, the maximum cclk frequency should be less than 128 fso and less than 128 fsi. this is dictat ed by the timing requirements necessary to access the channel status and user bit buffer memory. access to the control register file can be carried out at the full 6 mhz rate. the minimum allowable input sample rate is 8 khz, so choosing cclk to be less than or equal to 1.024 mhz should be safe for all possible conditions. 14. data must be held for sufficient time to bridge the transition time of cclk. 15. for f sck < 1 mhz. parameter symbol min typ max units cclk clock frequency (note 13) f sck 0-6.0mhz cs high time between transmissions t csh 1.0 - - s cs falling to cclk edge t css 20 - - ns cclk low time t scl 66 - - ns cclk high time t sch 66 - - ns cdin to cclk rising setup time t dsu 40 - - ns cclk rising to data hold time (note 14) t dh 18 - - ns cclk falling to cdout stable t pd - - 45 ns rise time of cdout t r1 - - 25 ns fall time of cdout t f1 - - 25 ns rise time of cclk and cdin (note 15) t r2 --100ns fall time of cclk and cdin (note 15) t f2 --100ns t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t pd cdout t csh figure 3. spi mode timing
ds245f4 11 cs8420 switching characteristics - control port - i2c ? mode inputs: logic 0 = 0 v, logic 1 = vd+; c l = 20 pf. 16. data must be held for suffi cient time to bridge the 25 ns transition time of scl. parameter symbol min typ max units scl clock frequency fscl - - 100 khz bus free time between transmissions t buf 4.7 - - s start condition hold time (p rior to first clock pulse) t hdst 4.0 - - s clock low time t low 4.7 - - s clock high time t high 4.0 - - s setup time for repeated start condition t sust 4.7 - - s sda hold time from scl falling (note 16) t hdd 0- - s sda setup time to scl rising t sud 250 - - ns rise time of both sda and scl lines t r - - 25 ns fall time of both sda and scl lines t f - - 25 ns setup time for stop condition t susp 4.7 - - s t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop start start stop repeated sda scl figure 4. i2c mode timing
12 ds245f4 cs8420 2. typical connection diagram cs8420 cable te rm in a t i on rxp rxn aes3/ spdif source 3-wire serial audio source ilrck isclk sdin clock source and control rmck omck hardware control rst rerr emph tcbl to other cs8420's cable interface aes3/ spdif equipment txp txn 3-wire serial audio input device olrck osclk sdout microcontroller sda/cdout ad0 / cs scl/cclk ad1/cdin u int va+ vd+ ferrite * bead +5v analog supply * +5v digital supply 0.1 f 0.1 f * a separate analog supply is only necessary in applications where rmck is used for a jitter sensitive task. for applications where rmck is not used for a jitter sensitive task, connect va+ to vd+ via a ferrite bead. keep the decoupling capacitor between va+ and agnd. dgnd filt agnd rfilt cfilt crip h/s 47k /ad2 figure 5. recommended connection diagram for software mode
ds245f4 13 cs8420 3. general description the cs8420 is a fully asynchronous samp le rate converter plus aes3 transceiver intended to be used in digital au- dio systems. such systems include digital mixing consoles , effects processors, tape recorders, and computer mul- timedia systems. the cs8420 is intended for 16-, 20-, an d 24-bit applications where the input sample rate is unknown, or is known to be asyn chronous to the sys tem sample rate. on the input side of the cs8420, aes3 or 3-wire serial format can be chos en. the output side produces both aes3 and 3-wire serial format. an i2c/spi-compatible microcontro ller interface allows full blo ck processing of channel sta- tus and user data via block reads from the incoming aes3 data stream and block writ es to the outgoing aes3 data stream. the user can also access information decoded fr om the input aes3 data stream, such as the presence of non-audio data and pre-emphasis, as well as control the va rious modes of the device. for users who prefer not to use a micro-controller, six hardware modes have been prov ided and documented towards the end of this data sheet. in these modes, flexibility is limited, wi th pins providing some programmability. when used for aes3-input/aes3 -output applications, the cs842 0 can automatically transceive user data that con- forms to the iec60958-recommended format. the cs8420 also allows access to the rele vant bits in the aes3 data stream to comply with the serial copy management system (scms). the diagram on the cover of this data sheet s hows the main functional blocks of the cs8420. figure 5 shows the supply and external connections to the device. familiarity with the aes3 and iec60958 specifications are assu med throughout th is document. application note 22: overview of digital audio interface data structures , contains a tutorial on digital audio specifications. the paper an understanding and implementation of the scms serial copy management system for digital audio transmission , by clif sanchez, is an excellent tutorial on scms. it may be obtained from ci rrus logic, inc., or from the aes. to guarantee system compliance, the proper standard s documents should be obtain ed. the latest aes3 standard should be obtained from the audio engineering society (ans i), the latest iec60958 standard from the international electrotechnical commission and the latest eiaj cp -1201 standard from the japanese electronics bureau.
14 ds245f4 cs8420 4. data i/o flow and clocking options the cs8420 can be configured for nine connectivity alternatives, referred to as data flows. each data flow has an associated clocking set-up. figure 6 shows the data flow switching, along with the control register bits which control the switches. this drawing only shows the audio data paths for simplicity. figure 7 shows the internal clock routing and the associated control register bits. the clock routin g constraints determine which data routing options are ac- tually usable. serial audio input aes3 encoder serial audio output receiver sample rate converter rxp rxn ilrck isclk sdin olrck osclk sdou t txp txn aes3 txoff aesbp spd1-0 txd1-0 srcd figure 6. software mode audio data flow switching options sims pll txp txn sdout osclk olrck omck rmck rxp ilrck isclk sdin mux mux mux swclk unlock 0 1 0 1 0 1 channel status memory user bit memory transmit aes3 serial audio output inc rxd0 mux 0 1 outc serial audio input rxd1 mux 0 1 clk[1:0] rmckf sample rate converter figure 7. cs8420 clock routing *note: when swclk mode is enabled, signal input on omck is only output through rmck and not routed back through the rxd1 multiplexer; rmck is not bi-directional in this mode.
ds245f4 15 cs8420 the aesbp switch allows a ttl level, bi -phase mark-enco ded data stream connected to rxp to be routed to the txp and txn pin drivers. the txoff switch causes the txp and txn outputs to be driven to ground in modes including the src function, there are two audio-data-related clock domains. one domain includes the in- put side of src, plus the at tached data source. the second domain inclu des the output side of the src, plus any attached output ports. there are two possible clock sources. the first known as th e recovered clock, is the output of a pll, and is con- nected to the rcmk pin. the input to the pll can be either the incoming aes3 data stream or th e ilrck word rate clock from the serial audio input port. the second clock is input via the omck pin, and would normally be a crystal- derived stable clock. the clock source control register bits determine which clock is connected to which domain. by studying the following drawings, and appropriately se tting the data flow control and clock source control reg- ister bits, the cs8420 can be configured to fit a variety of application requirements. the following drawings illustrate the possibl e valid data flows. the aud io data flow is indicated by the thin lines; the clock routing is indicated by the bold lines. the register settings for the data flow control register and the clock source register are also shown for each data flow. some of the register settings may appear to be not relevant to the particular data flow in question, but have been assig ned a particular state. this is done to minimize power con- sumption. the aesbp data path from the rxp pin to the aes3 output drivers, and the txoff co ntrol, have been omitted for clarity, but are present and functional in all modes where the aes3 transmitter is in use. figures 8 and 9 show audio data entering via the serial audio in put port, then passing through the sample rate con- verter, and then output both to the serial audio output port and to the aes3 transmitter. figure 8 shows the pll recovering the input clock from ilrck word clock. figure 9 shows using a direct 256*fsi clock input via the rmck pin, instead of the pll. figure 10 shows audio data entering via the aes3 receiver. th e pll locks onto the pre- ambles in the incoming audio stream, and generates a 256*fsi cl ock. the rate-converted data is then output via the serial audio output port and via the aes3 transmitter. figure 11 shows the same data flow as figure 8 . the input clock is derived from an incoming aes3 data stream. the incoming data must be synchronous to the aes3 data stream. figure 12 shows the same data flow as figure 8 . the input data must be synchronous to omck. the output data is clocked by the recovered pll clock from an aes3 input stream. this may be used to implement a ?house sync? architecture. figure 8 shows audio data entering via the aes3 receiver, passing thro ugh the sample rate co nverter, and then ex- iting via the serial audio output port. synchronous audio data may then be input via the serial audio input port and output via the aes3 transmitter. figure 14 is the same as figure 13 , but without the sample rate converter. the whole data path is clocked via the pll generated recovered clock. figure 15 illustrates a standard aes3 receiver function, with no rate conversion. figure 16 shows a standard aes3 transmitter function, with no rate conversion.
16 ds245f4 cs8420 figure 8. serial audio input, using pll, src enabled figure 9. serial audio input, no pll, src enabled serial audio input aes3 encoder &driver serial audio output sample rate converter ilrck isclk sdin olrck osclk sdou t txp txn pll rmck omck txd1-0: spd1-0: srcd: outc: inc: rxd1-0: 00 00 0 0 0 00 clock source control bits data flow control bits serial audio input aes3 encoder &driver serial audio output sample rate converter ilrck isclk sdin olrck osclk sdou t txp txn rmck omck txd1-0: spd1-0: srcd: outc: inc: rxd1-0: 00 00 0 0 0 1 0 clock source control bits data flow control bits aes3 encoder &driver serial audio output sample rate converter olrck osclk sdou t txp txn pll rmck omck txd1-0: spd1-0: srcd: outc: inc: rxd1-0: 00 00 1 0 0 0 1 clock source control bits data flow control bits aes3 rx & decode rxp rxn serial audio input aes3 encoder &driver serial audio output sample rate converter ilrck isclk sdin olrck osclk sdou t txp txn pll rmck omck txd1-0: spd1-0: srcd: outc: inc: rxd1-0: 00 00 0 0 0 0 1 clock source control bits data flow control bits aes3 rx rxp rxn figure 10. aes3 input, src enabled figure 11. serial audio input, aes3 input clock source, figure 12. serial audio input, src output clocked by aes3 recovered clock figure 13. aes3 input, src to serial audio output, serial audio input to aes3 out aes3 encoder &driver serial audio output sample rate converter txp tx n pll rmck omck txd1-0: spd1-0: srcd: outc: inc: rxd1-0: 01 00 1 0 0 0 1 clock source control bits data flow control bits aes3 rx & decode rxp rxn serial audio input olrck osclk sdout ilr c k isclk sdin serial audio input aes3 encoder &driver serial audio output sample rate converter ilrck isclk sdin olrck osclk sdou t txp txn pll rmck omck txd1-0: spd1-0: srcd: outc: inc: rxd1-0: 00 00 0 1 1 0 1 clock source control bits data flow control bits aes3 rx rxp rxn
ds245f4 17 cs8420 figure 14. aes3 input to serial audio output, serial au- dio input to aes3 out, no src figure 15. aes3 input to serial audio output only aes3 encoder &driver serial audio output olrck osclk sdout txp tx n pll rmck txd1-0: spd1-0: srcd: outc: inc: rxd1-0: 01 10 0 1 0 0 1 clock source control bits data flow control bits aes3 rx & decode rxp rxn serial audio input ilrck isclk sdin serial audio output olrck osclk sdou t pll rmck txd1-0: spd1-0: srcd: txoff: outc: inc: rxd1-0: 10 10 0 1 1 0 01 clock source control bits data flow control bits aes3 rx & decode rxp rxn serial audio input aes3 encoder &driver ilrck isclk sdin txp tx n omck txd1-0: spd1-0: srcd: outc: inc: rxd1-0: 01 01 0 0 1 00 clock source control bits data flow control bits figure 16. input serial port to aes3 transmitter
18 ds245f4 cs8420 5. sample rate converter (src) multirate digital signal processing techni ques are used to conceptually upsample the incoming data to very high rate and then downsample to the outgoing rate, resulting in a 24-bit output, regardless of the width of the input. the fil- tering is designed so that a full input audio bandwidth of 20 khz is preserved if the input sample and output sample rates are greater than 44.1 khz. when the output sample rate becomes less than the input sample rate, the input is automatically band limited to avoid aliasing products in the output. careful design ensures minimum ripple and dis- tortion products are added to the incoming signal. the src also determines the ratio between the incoming and outgoing sample rates, and sets the filter corner frequencie s appropriately. any jitter in the incoming signal has little impact on the dynamic performance of the rate converter and has no influence on the output clock. 5.1 dither when using the aes3 input, and when using the serial audio input port in left-justified and i2s modes, all input data is treated as 24 bits wide. any truncation th at has been done prior to the cs8420 to less than 24 bits should have been done using an appropriate dither pr ocess. if the serial audio input port is used to feed the src, and the port is in right-jus tified mode, then the input data will be truncated to the sires bit setting value. if sires bits are set to 16 or 20 bits, and the input da ta is 24 bits wide, trun cation distortion will occur. similarly, in any serial audio input port mode, if an i nadequate number of bit clocks are entered (say 16 in- stead of 20), the input words will be truncated, causing trunca tion distortion at low levels. in summary, there is no dithering mechanism on the input side of the cs 8420, and care must be taken to ensure that no trun- cation occurs. dithering is used internally where appropriate inside the src block. the output side of the src can be set to 16, 20, or 24 bits. optional dithering can be applied, and is auto- matically scaled to the selected output word length. this dither is not corr elated between left and right chan- nels. it is recommended that the dither control bit be left in its default on state. 5.2 src locking, varispeed and th e sample rate ratio register the src calculates the ratio between the input sample ra te and the output sample rate and uses this infor- mation to set up various parameters inside the src bl ock. the src takes some time to make this calcula- tion. for a worst case 3:1 to 1:3 in put sample rate transition, the sr c will take 9400/fso to settle (195 ms at fso of 48 khz). for a po wer-up situation, the s rc will start from 1:1; the worst case time becomes 8300/fso (172 ms at fso of 48 khz). if the pll is in use (either aes3 or serial input port), the worst case locking time for the pll and the src is the sum of each locking time. if fsi is changing, for example in a varispeed application, the reunlo ck interrupt will occur, and the src will track the incoming sample rate. du ring this tracking mode, the src will still rate convert the audio data, but at increased distortion levels. once the incoming sample rate is stable, th e reunlock interrupt will become false, and the src will return to normal levels of audio quality. the vfifo interrupt occu rs if the data buffer in the src overflows, which can occur if the input sample rate changes at >10%/second. varispeed at fsi slew rates approaching 10%/sec is on ly supported when the input is via the serial audio input port. when using the aes3 in put, high frame rate slew rates will cause the pl l to lose lock. the sample rate ratio is also made available as a r egister, accessible via the control port. the upper 2 bits of this register form the integer part of the ratio, while the lower 6 bits form the frac tional part. since, in many instances fso is known, this allows the calculation of the incoming sample rate by the host microcontroller.
ds245f4 19 cs8420 6. three-wire serial audio ports a 3-wire serial audio input port and a 3-wire serial audio output port is provided. each port can be adjusted to suit the attached device via control registers. the following parameters are adjustable: master or slave, serial clock fre- quency, audio data resolution, left or right justification of the data relative to left/right clock, optional 1-bit cell delay of the 1st data bit, the polarity of the bit clock and the polarity of the left/right clock. by setting the appropriate control bits, many formats are possible. figure 17 shows a selection of common input formats, along wit h the control bit settings. the clocking of the input section of the cs8420 may be derived from the incoming ilrck word rate clock, using the on-chip pll. the pll operation is described in the aes receiver description on page 22 . in the case of use with the serial audio input port, the pll locks onto the leading edges of the ilrck clock. figure 18 shows a selection of co mmon output fo rmats, along with the c ontrol bit settings. a special aes3 direct output format is included, which allows serial output port access to the v, u, and c bits embedded in the serial audio data stream. the p bit is replaced by a bit indicating the locati on of the start of a block. th is format is only available when the serial audio output port is being clocked by the aes3 re ceiver-recover ed clock. also, th e received-channel status block start signal is only availa ble in hardware mode 5, as the rcbl pin. in master mode, the left/right clock and the serial bit cl ock are outputs, derived from the appropriate clock domain master clock. in slave mode, the left/right clock and the serial bit clock are inputs. the left/right clock must be synchronous to the appropriate master clock, but the seri al bit clock can be asynchronous and di scontinuous if required. by appropriate phasing of the left/right clock and control of the serial clocks, multiple cs8420?s can share one serial port. the left/right clock should be continuous, but the duty cycle does not have to be 50%, provided that enough serial clocks are present in each phase to clock all the data bits. when in slave mode, the serial audio output port must be set to left-justified or i2s data. when using the serial audio output port in slave mode with an olrck input which is asynchronous to the port?s data source, then an interrupt bit is provided to indicate when repeated or dropped samples occur. the cs8420 allows immediate mute of the serial audio output port audio data via a control register bit.
20 ds245f4 cs8420 figure 17. serial audio input example formats msb lsb msb lsb msb ilrck isclk sdin channel a channel b left justified (in) ilrck isclk msb lsb msb lsb channel a sdin msb channel b i2s (in) ilrck isclk channel a channel b msb sdin msb lsb lsb right justified (in) x = don?t care to match format, but does need to be set to the desired setting + i2s can accept an arbitrary number of bi ts, determined by the number of isclk cycles * not 11 - see serial input port data fo rmat register bit descript ions for an explanation of the meaning of each bit sims sisf sires1/0 sijust sidel sispol silrpol left-justified x x 00 0 0 0 0 i2s xx00+0101 right-justified x x xx* 1 0 0 0
ds245f4 21 cs8420 figure 18. serial audio output example formats x = don?t care to match format, but does need to be set to the desired setting * not 11 - see serial output data format register bit descriptions for an explanation of the meaning of each bit soms sosf sores1/0 soju st sodel sospol solrpol left-justified x x xx* 0 0 0 0 i2s xxxx*0101 right-justified 1 x xx* 1 0 0 0 aes3 directxx110000 olrck osclk sdout channel a channel b left justified (out) olrck osclk channel a sdout channel b i2s (out) olrck osclk channel a channel b msb sdout msb lsb lsb msb extended msb extended right justified (out) olrck osclk channel a channel b msb sdout lsb lsb channel a channel b lsb lsb msb msb msb aes3 direct (out) msb msb msb lsb lsb msb lsb msb lsb msb c u v z c u v c u v c u v frame 191 frame 0 z
22 ds245f4 cs8420 7. aes3 transmitter and receiver the cs8420 includes an aes3-type digi tal audio receiver and an aes3-type di gital audio transmitter. a compre- hensive buffering scheme provides read/write access to the channel status and user data. this buffering scheme is described in ?channel status and user data buffer management? on page 81 . 7.1 aes3 receiver the aes3 receiver accepts and decode s audio and digital data accordin g to the aes3, iec60958 (s/pdif), and eiaj cp-1201 interface standards. the receiver consists of a differen tial input stage, accessed via pins rxp and rxn, a pll based clock recovery circuit, a nd a decoder which separates the audio data from the channel status and user data. external components are used to terminate and isol ate the incoming data cables from the cs8420. these components are detailed in ?external aes3/spdif/iec6 0958 transmitter and rece iver components? on page 78 . 7.1.1 pll, jitter attenuation, and varispeed please see ?pll filter? on page 87 for general description of the pll, selection of recommended pll filter components, and layout considerations. figure 5 shows the recommended configuration of the two ca- pacitors and one resistor that comprise the pll filter. 7.1.2 omck out on rmck a special mode is available that allows the clock that is being input through the omck pin to be output through the rmck pin. this feature is controlled by the swclk bit in register 4 of the control registers. when the pll loses lock, the frequency of the vco drops to 300 khz. the swclk function allows the clock from rmck to be used as a clock in the system without any disruption when input is removed from the receiver. 7.1.3 error reporting and hold function while decoding the incoming aes3 data stream, the cs84 20 can identify several kinds of error, indicated in the receiver error r egister. the unlock bit indicates whether the pll is locked to the incoming aes3 data. the v bit reflects th e current validity bit status . the conf (confidence) bit indicates the amplitude of the eye pattern opening, indicating a link that is close to generating errors. the bip (bi-phase) error bit indicates an error in incoming bi-phase coding. the pa r (parity) bit indicates a received parity error. the error bits are ?sticky? - they are set on the firs t occurrence of the associat ed error and will remain set until the user reads the register via the control port. this enables the register to log all unmasked errors that occurred since the last time the register was read. the receiver error mask register allo ws masking of individual errors. the bits in this register serve as masks for the corresponding bits of the receiver error re gister. if a mask bit is set to 1, the error is con- sidered unmasked, meaning th at its occurrence will be reported in the receiver error register, will affect the rerr pin, will invoke the occurrence of a rerr interrupt, and will affect the current audio sample according to the status of the hold bits. the hold bits allow a choice of holding the previous sample, replacing the current sample with zero (mute), or do not change the current audio sample. if a mask bit is set to 0, the error is considered masked, meaning th at its occurrence will not be reported in the receiver error register, will not induce a pulse on rerr or generate a rerr interr upt, and will not affect the current audio sample. the qcrc and ccrc er rors do not affect the current audio sample, even if unmasked.
ds245f4 23 cs8420 7.1.4 channel status data handling the first 2 bytes of the channel status block are deco ded into the receiver channel status register. the setting of the chs bit in the channel status data bu ffer control register determines whether the channel status decodes are from the a channel (chs = 0) or b channel (chs = 1). the pro (professional) bit is extrac ted directly. also, for consumer dat a, the copy (copyright) bit is ex- tracted, and the category code and l bits are dec oded to determine scms stat us, indicated by the orig (original) bit. finally, the audio bit is extracted, and used to set an audio indicator, as described in the non-audio auto detection section below. if 50/15 s pre-emphasis is detected, then this is reflected in the state of the emph pin. the encoded sample word length ch annel status bits are decoded accordi ng to aes3-1992 or iec 60958. if the aes3 receiver is th e data source for the src, then the src audio input data is truncated according to the channel status word length settings. audio data routed to the serial audio output port is unaffected by the word length settings; all 24 bits are passed on as received. ?channel status and user data buffer management? on page 81 describes the overall handling of cs and u data. 7.1.5 user data handling the incoming user data is buffered in a user-acces sible buffer. various automatic modes of re-transmit- ting received u data are provided. ?channel status and user data buffer management? on page 81 de- scribes the overall handling of cs and u data. received u data may also be output to the u pin, un der the control of a control register bit. depending on the data flow and clocking options selected, there may not be a clock available to qualify the u data output. figure 19 illustrates the timing. if the incoming user data bits have been encoded as q-channel subcode, the data is decoded and pre- sented in 10 consecutive register locations. an interr upt may be enabled to indicate the decoding of a new q-channel block, which may be read via the control port. rcbl out vlrck c, u output rcbl and c output are only available in hardware mode 5. rcbl goes high 2 frames after receipt of a z pre-amble, and is high for 16 frames. vlrck is a virtual word clock, which may not exist, but is used to illustrate the cu timing. vlrck duty cycle is 50%. vlrck frequency is always equal to the incoming frame rate. if no src is used, and the serial audio output port is in master mode, vlrck = olrck. if the serial audio output port is in slave mode, t hen vlrck needs to be externally created, if required. c, u transitions are ali g ned within 1% of vlrck p eriod to vlrck ed g es figure 19. aes3 re ceiver timing for c & u pin output data
24 ds245f4 cs8420 7.1.6 non-audio au to detection since it is possible to convey non-audio data in an aes3 data stream, it is important to know whether the incoming aes3 data stream is digita l audio or other data. this informat ion is typically conveyed in channel status bit 1 (audio ), which is extracted automatically by the cs8420. however, certain non-audio sourc- es, such as ac-3 ? or mpeg encoders, may not adhere to this convention, and the bit may not be properly set. the cs8420 aes3 re ceiver can detect such no n-audio data. this is acco mplished by looking for a 96-bit sync code, consisting of 0x0000, 0x0000, 0x0000, 0x0000, 0xf872, and 0x4e1f. when the sync code is detected , an internal autodetect signal will be as serted. if no addition al sync codes are de- tected within the next 4096 fram es, autodetect will be de-asserted until another sync code is detect- ed. the audio bit in the receiver channel status register is the logica l or of autodetect and the received channel status bit 1. if non-audio data is de tected, the data is still processed exactl y as if it were normal audio. it is up to the us er to mute the outputs as required. 7.2 aes3 transmitter the aes3 transmitter encode s and transmits audio and digital data according to the aes3, iec60958 (s/pdif), and eiaj cp-1201 interface standards. audio and control data are multiplexed together and bi-phase mark-encoded. the resulting bit stream is t hen driven directly, or through a transformer, to an output connector. the transmitter is usually clocked from the output side clock domain of the sample rate converter. this clock may be derived from the clock input pin omck, or from the incoming data. in data flows with no src, and where omck is as ynchronous to the data source, an interrupt bi t is provided that will go high every time a data sample is dropped or repeated. the channel status (c) and user channel (u) bits in the transmitted data stream are taken from storage areas within the cs8420. the user can manipulate t he contents of the internal storage with a microcon- troller. the cs8420 will also run in one of several aut omatic modes. ?channel status and user data buffer management? on page 81 provides detailed descriptions of each automatic mode, and describes methods for accessing the storage areas. the transmitted user data can optionally be input via the u pin, under the control of a control port register bit. figure 20 shows the timing requirements for inputting u data via the u pin. 7.2.1 transmitted frame and ch annel status boundary timing the tcbl pin may be an input or an output, and is used to control or indicate the start of transmitted chan- nel status block boundaries. in some applications, it may be necessary to control the precise timing of the transmitted aes3 frame boundaries. this may be achieved in 3 ways: 1) with tcbl configured as an input, and tcbl tr ansitions high for >3 omck clocks, it will cause a frame start, and a new channel status block start. 2) if the aes3 output comes from th e aes3 input, while there is no src, setting tcbl as output will cause aes3 output frame boundaries to alig n with aes3 input frame boundaries. 3) if the aes3 output comes from th e serial audio input port while the port is in slave mode, and tcbl is set to output, then the start of the a channel sub-frame will be alig ned with the leadin g edge of ilrck.
ds245f4 25 cs8420 7.2.2 txn and txp drivers the line drivers are low-skew, low-impedance, differential outputs capable of driving cables directly. both drivers are set to ground during reset (rst = low), when no aes3 transmit clock is provided, and option- ally under the control of a regist er bit. the cs8420 also allows imme diate mute of t he aes3 transmitter audio data via a control register bit. external components are used to terminate and isolat e the external cable from the cs8420. these com- ponents are detailed in ?external aes3/spdif/iec60958 transmitter and receiver components? on page 78 . 7.3 mono mode operation currently, the aes3 st andard is being upda ted to include options for 96-k hz sample rate operation. one method is to double the frame rate of the current format. this results in a 96-khz sample rate, stereo signal carried over a single twisted pair cable. an alternate method is where the 2 sub-frames in a 48-khz frame rate aes3 signal are used to carry consecutive samp les of a mono signal, resulting in a 96-khz sample rate stream. this allows older equipmen t, whose aes3 tran smitters and re- ceivers are not rated for 96-khz frame rate operation, to handle 96-khz sample rate information. in this ?mono mode?, 2 aes3 cables are n eeded for stereo data transfer. th e cs8420 offers mono mode opera- tion, both for the aes3 receiver and for the aes3 transmitter. figure 21 shows the operation of mono mode in comparison with normal stereo mode. the receiver and transmitter sections may be independently set to mono mode via the mmr and mmt control bits. the receiver mono mode effectively doubles fsi compared to the input frame rate. the clock output on the rmck pin tracks fsi, and so is doubled in frequency compared to stereo mode. in mono mode, a and b sub-frames are routed to the src inputs as consecutive samples. when the transmitter is in mono mo de, either a or b src consecutive outputs are routed alternately to a and b sub-frames in the aes3 output stream. which chan nel status block is transm itted is also selectable. for the aes3 input to serial audio po rt output data flow, in receiver mono mode, then the receiver will run at a frame rate of fsi/2, and the se rial audio output port will run at fs i. identical data will appear in both left and right data fields on the sdout pin. for the serial audio input port to aes3 transmitter data flow, in trans mitter mono mode, then the input port will run at fso audio sample rate, wh ile the aes3 transmitter frame rate will be at fso/2. the data from either consecutive left, or right, posi tions will be selected for transm itting in a and b sub-frames.
26 ds245f4 cs8420 figure 20. aes3 transmitter timing for c, u and v pin input data vcu[0] vcu[1] vcu[2] vcu[3] vcu[4] data [4] data [5] data [6] data [7] data [8] data [0] data [1] data [2] data [3] data [4] z y x y x aes3 transmitter in stereo mode u[0] u[2] vlrck data [4] data [5] data [6] data [7] data [8] data [0]* data [2]* data [4]* z y x *assume mmtlr = 0 tsetup = > 7.5 % aes3 frame time thold = 0 tsetup thold data [1]* data [3]* data [5]* zy x aes3 transmitter in mono mode *assume mmtlr = 1 tsetup = > 15 % aes3 frame time thold = 0 tth tth > 3 omck if tcbl is input tth > 3 omck if tcbl is input tth u input tcbl in or out sdin input txp(n) output txp(n) output vlrck vcu input sdin input tcbl in or out txp(n) . vlrck duty cycle is 50% in stereo mode, vlrck frequency = aes3 frame rate. in mono mode, alrck frequency = 2xaes3 frame rate. if the serial audio input port is in master mode and tcbl is an input, the vlrck=ilrck if silrpol=0 and vlrck is a virtual word clock, which may not exist, and is used to illustrate cuv timing. if the serial audio input port is in slave mode and tcbl is an output, the vlrck=ilrck if silrpol=0 and vlrck= ilrck if silrpol = 1. vlrck= ilrck if silrpol = 1.
ds245f4 27 cs8420 src aes3 receiver aes3 transmitter pll in out aa aa bb bb 96khz stereo 96khz frame rate 256x96khz 96khz stereo 96khz frame rate 96khz fsi 96khz fso omck (256, 384, or 512x 96khz) src aes3 receiver aes3 transmitter pll (x2) in out aa aa bb bb 96khz mono 48khz frame rate 256x96khz 96khz mono 48khz frame rate 96khz fsi 96khz fso omck (256, 384, or 512x 96khz) * + a & b sub-frames data are time-multiplexed into consecutive samples consecutive samples are alternately route d to a & b sub-fames *+ receiver mono mode re c eiver stereo mode mmtlr tran s mitter stereo mode transmitter mono mode a1 b1 outgoing aes3 src aout src bout a1 b1 a2 b2 stereo mono frame a2 b2 outgoing aes3 a selected outgoing aes3 b se l ected a1 a2 b1 b2 frame transmitter timing figure 21. mono mode operation co mpared to normal stereo operation a1 b1 a2 b2 incoming aes3 src ain src bin ain & bin s r c a1 a1 b1 b1 a2 b2 a2 b2 stereo mono frame receiver timing
28 ds245f4 cs8420 8. aes3 transmitter and receiver 8.1 sample rate converter the equation for the group delay through the sample rate converter, with the serial ports in master mode is: ((input interface delay + 43) / f si ) + ((43 + output interface delay 0.5) / f so ) the unit of delay depends on the frame rate (sample rate) f s . the aes receiver has a interface delay of 2 frames. the aes transmitter, the serial input port, and the serial output port each have an interface delay of 1 frame. the 0.5 frame delay in the second half of the equation is due to the start-up uncertainty of the logic within the part. when using multiple parts to gether, it is possible to start the parts simultaneously in a fashion that minimizes the relative group delay between the parts. when multiple parts are started together in the proper way, the variation in signal delay through the parts is 1.5 s. to start the parts simu ltaneously, set up each one so that the pll will lock, with the active input port driving both output ports. then simultaneously enable the run bits in all of the parts. tcbl on one of the cs8420 parts should be set as an output, while the remaining tcbl pins should be set as inputs. this synchronizes the aes transmitter on all of the parts. depending upon software considerations, it may be ad vantageous to configure the registers so that an in- terrupt is generated on the int pin when lock occurs. the control logic should either poll the unlock bits until all pll?s are locked or wait for t he interrupts to indicate that all ar e locked, depending on which approach you?ve chosen. when all of the pll?s are locked, the cs8420?s should be advanced to the next state together. drive all the serial control ports together with the same clock and data. change the configuration in register 03h accord- ing to ta b l e 1 or ta b l e 2 . table 1. minimizing group delay through multiple cs8420s when locking to rxp/rxn table 2. minimizing group delay through multiple cs8420s when locking to ilrck register (hex) initial value (hex) value after advancing to the running state, after the pll?s are locked (hex) 01 01 or 00 01 or 00 03 95 81 04 41 41 11 10 10 register (hex) initial value (hex) value after advancing to the running state, after the pll?s are locked (hex) 01 01 or 00 01 or 00 03 8a 80 04 40 40 11 10 10
ds245f4 29 cs8420 8.2 non-src delay the unit of delay depends on the frame rate (sample rate) f s . the aes receiver has a interface delay of two frames. the aes tr ansmitter, the serial input po rt, and the serial ou tput port each have an interface delay of 1 frame. the 0.5 frame delay in the second half of the equation is due to the startup uncertainty of the logic within the part. 1. all inputs are slaves and all outputs are ma sters, both with respect to the outside world. 2. the inputs and outputs are synchronous to one another. path delay (in units of a frame) rx to tx 3 1/128 serial input to tx 2 1/128 rx to serial output 3 1/128 serial input to serial output 2 1/128 table 3. non-src delay
30 ds245f4 cs8420 9. control port desc ription and timing the control port is used to access the registers, allowin g the cs8420 to be configured for the desired operational modes and formats. in addition, channel status and user data may be read and written via the control port. the operation of the control port may be completely asynchr onous with respect to the audio sample rates. however, to avoid potential interference problems, the control port pi ns should remain static if no operation is required. the control port has two modes: spi and i2c, with the cs 8420 acting as a slave device. spi mode is selected if there is a high-to-low transition on the ad0/cs pin after the rst pin has been brought high. i2c mode is selected by connecting the ad0/cs pin to vd+ or dgnd, thereby permanently se lecting the desired ad0 bit address state. 9.1 spi mode in spi mode, cs is the cs8420 chip select signal. cclk is th e control port bit clock (input into the cs8420 from the microcontroller), cdin is the input data line from the microcontro ller, cdout is the output data line to the microcontroller. data is clocked in on th e rising edge of cclk and out on the falling edge. figure 22 shows the operation of the control port in spi mode. to write to a register, bring cs low. the first 7 bits on cdin form the chip address and must be 001 0000b. the eighth bit is a read/write indicator (r/w ), which should be low to write. the next 8 bits form the memory address pointer (map), which is set to the address of the register that is to be updated. the next 8 bits are the data which will be placed in to the register designated by the map. during writes , the cdout output stays in the hi-z state. it may be externally pulled high or low with a 47 k resistor, if desired. there is a map auto-increment capabilit y, enabled by the incr bit in the map register. if incr is a zero, then the map will stay const ant for successive read or writes. if incr is set to a 1, th en the map will auto- increment after each byte is read or written, allo wing block reads or writes of successive registers. to read a register, the map has to be set to the correct address by executing a partial write cycle which finishes (cs high) immediately after the m ap byte. the map auto-increment bit (incr) may be set or not, as desired. to begin a read, bring cs low, send out the chip address and set the read/write bit (r/w ) high. the next falling edge of cclk will clock out the msb of the addressed register (cdout will leave the high- impedance state). if the map auto-increment bit is se t to 1, the data for successive registers will appear consecutively. map msb lsb data byte 1 byte n r/w r/w address chip address chip cdin cclk cs cdout msb lsb msb lsb 0010000 0010000 map = memor y address pointer, 8 bits, msb first high impedance figure 22. control port timing in spi mode
ds245f4 31 cs8420 9.2 i2c mode in i2c mode, sda is a bidirectional data line. data is clocked in to and out of the part by the clock, scl, with the clock to data rela tionship as shown in figure 23 . there is no cs pin. each individual cs8420 is given a unique address. pins ad[1:0] form the two least signific ant bits of the chip address and should be connected to vd+ or dgnd as desired. the emph pin is used to set the ad2 bit, by connecting a resistor from the emph pin to vd+ or to dgnd. the state of the pin is sensed while the cs8420 is being reset. the upper four bits of the 7-bit addre ss field are fixed at 0010b. to communicate with a cs8420, the chip address field, which is the first byte sent to the cs8420, shoul d match 0010b followed by the settings of the emph , ad1, and ad0. the eighth bit of the address is the r/w bit. if the operation is a write, the next byte is the memory address pointer (map) which selects th e register to be read or written. if the operation is a read, the con- tents of the register point ed to by the map will be output. setting t he auto-increment bit in map allows suc- cessive reads or writes of consecutive registers. each byte is separated by an acknowledge bit. the ack bit is output from the cs8420 after each input byte is read and is input to the cs8420 from the microcon- troller after each transmitted byte. 9.3 interrupts the cs8420 has a comprehensiv e interrupt capability. the int output pin is intended to drive the interrupt input pin on the host microcontroller. the int pin may be set to be active-low, active-high, or active-low with no active pull-up transistor. this last mode is used for active-low, wired-or hook -ups, with multiple periph- erals connected to the microcontroller interrupt input pin. many conditions can cause an interrupt, as listed in th e interrupt status register descriptions. each source may be masked via mask registers. in addition, each source may be set to rising-edge, fallin g-edge, or level- sensitive. combined with the option of level-sensitive or edge-sensitive modes within the microcontroller, many different set-ups are possible, depending on the needs of the equipment designer. sda scl 0010 ad2-0 r/w start ack data7-0 ack data7-0 ack stop note 2 note 1 note 3 figure 23. control port timing in i2c mode 1. ad2 is derived from a resistor attached to the emph pin ad1, and ad0 are determined by the state of the corresponding pins. 2. if operation is a write, this byte co ntains the memory address pointer, map. 3. if operation is a read, the last bi t of the read should be nack (high). notes:
32 ds245f4 cs8420 10. control port register bit definitions 10.1 memory address pointer (map) this register defaults to 01 incr auto-increment address control bit 0 - auto-increment address off 1 - auto-increment address on map6-map0 register address and function list 0 - reserved 1 - misc. control 1 2 - misc. control 2 3 - data flow control 4 - clock source control 5 - serial audio input port data format 6 - serial audio output port data format 7 - interrupt register 1 status 8 - interrupt register 2 status 9 - interrupt register 1 mask 10 - interrupt register1 mode (msb) 11 - interrupt register 1 mode (lsb) 12 - interrupt register 2 mask 13 - interrupt register 2 mode (msb) 14 - interrupt register 2 mode (lsb) 15 - receiver channel status bits 16 - receiver error status 17 - receiver error mask 18 - channel status da ta buffer control 19 - user data buffer control 20 to 29 - q-channel subcode bytes 0 to 9 30 - sample rate ratio 31 - reserved 32 to 55 - c-bit or u-bit data buffer 56 to 126 - reserved 127 - chip id and version register reserved registers must not be written to during no rmal operation. some reserved registers are used for test modes, which can completely alte r the normal operation of the cs8420. 7 6 543210 incr map6 map5 map4 map3 map2 map1 map0
ds245f4 33 cs8420 addr (hex) function 7 6 5 4 3 2 1 0 01 control 1 swclk vset mutesao muteaes dith int1 int0 tcbld 02 control 2 trunc hold1 hold0 rmckf mmr mmt mmtcs mmtlr 03 data flow control amll txoff aesbp txd1 txd0 spd1 spd0 srcd 04 clock source control 0 run clk1 clk0 outc inc rxd1 rxd0 05 serial input format sims sisf sires1 sires0 sijust sidel sispol silrpol 06 serial output format soms sosf sores1 sores0 sojust sodel sospol solrpol 07 interrupt 1 status tslip oslip sre ovrgl ovrgr detc eftc rerr 08 interrupt 2 status 0 0 vfifo reunlock detu eftu qch uovw 09 interrupt 1 mask tslipm oslipm srem ovrglm ovrgrm detcm eftcm rerrm 0a interrupt 1 mode (msb) tslip1 oslip1 sre1 ovrgl1 ovrgr1 detc1 eftc1 rerr1 0b interrupt 1 mode (lsb) tslip0 oslip0 sre0 ovrgl0 ovrgr0 detc0 eftc0 rerr0 0c interrupt 2 mask 0 0 vfifom reunlockm detum eftum qchm uovwm 0d interrupt 2 mode (msb) 0 0 vfifo1 reunlock1 detu1 eftu1 qch1 uovw1 0e interrupt 2 mode (lsb) 0 0 vfifo0 reunlock0 detu0 eftu0 qch0 uovw0 0f receiver cs data aux3 aux2 aux1 aux0 pro audio copy orig 10 receiver errors 0 qcrc ccrc unlock v conf bip par 11 receiver error mask 0 qcrcm ccrcm unlockm vm confm bipm parm 12 cs data buffer control 0 0 bsel cbmr detci eftci cam chs 13 u data buffer control 0 0 0 ud ubm1 ubm0 detui eftui 14-1d q sub-code data 1e sample rate ratio srr7 srr6 srr5 srr4 srr3 srr2 srr1 srr0 20-37 c or u data buffer 7f id and version id3 id2 id1 id0 ver3 ver2 ver1 ver0 table 4. summary of all bits in the control register map
34 ds245f4 cs8420 10.2 miscellaneous control 1 (01h) swclk causes omck to be output through the rmck pin when the pll is unlocked 0 - rmck is driven by the pll vco (default) 1 - omck is switched to output through the rmck pin when the pll is unlocked. circuitry driv- en by the pll is driven by omck. vset transmitted v bit level 0 - transmit a 0 for the v bit, indicating that the data is valid, and is normally linear pcm audio (default) 1 - transmit a 1 for the v bit, indicating that the data is invalid or is not linear pcm audio data mutesao mute control for the serial audio output port 0 - normal output (default) 1 - mute the serial audio output port muteaes mute control for th e aes3 transmitter output 0 - normal output (default) 1 - mute the aes3 transmitter output dith dither control 0 - triangular pdf dither applied to output data. the level of the dither is automatically adjusted to be appropriate for the ou tput word length selected by the sores bits (default) 1 - no dither applied to output data. int[1:0] interrupt (int) output pin control 00 - active high, high output indicates an interrupt condition has occurred (default) 01 - active low, low output indicates an interrupt condition has occurred 10 - open drain, active low. this setting require s an external pull up resistor on the int pin. 11 - reserved tcbld transmit channel status bloc k pin (tcbl) direction specifier 0 - tcbl is an input (default) 1 - tcbl is an output 7 6 543210 swclk vset mutesao muteaes dith int1 int0 tcbld
ds245f4 35 cs8420 10.3 miscellaneous control 2 (02h) trunc determines whether the word length is set according to th e incoming channel status data 0 - data to the src is not truncated (default) 1 - data to the src is set according to the aux field in the incoming data stream hold[1:0] the hold bits determine how the receiv ed audio sample is affected when a receiver error occurs. 00 - hold the last valid audio sample (default) 01 - replace the current audio sample with 00 (mute) 10 - do not change the received audio sample 11 - reserved rmckf select recovered master clock output pin frequency. 0 - rmck is equal to 256 * fsi (default) 1 - rmck is equal to 128 * fsi mmr select aes3 receiver mo no or stereo operation 0 - interpret a and b subframes as two independ ent channels (normal stereo operation, default) 1 - interpret a and b subframes as consecutive samples of one channel of data.this data is duplicated to both left and right parallel outputs of the aes receiver block. the input sample rate (fsi) is doubled compared to mmr=0 mmt select aes3 transmitter mono or stereo operation 0 - outputs left channel input into a subframe and right channel input into b subframe (normal stereo operation, default). 1 - output either left or right channel inputs into consecutive subframe outputs (mono mode, left or right is determined by mmtlr bit) mmtcs select a or b channel status data to transmit in mono mode 0 - use channel a cs data for the a sub-frame slot and use channel b cs data for the b sub- frame slot (default) 1 - use the same cs data for both the a and b su b-frame output slots. if mmtlr = 0, use the left channel cs data. if mmtlr = 1, use the right channel cs data. mmtlr channel selection fo r aes transmitter mono mode 0 - use left channel input data for consecutive sub-frame outputs (default) 1 - use right channel input data for consecutive sub-frame outputs 7 6 543210 trunc hold1 hold0 rmckf mmr mmt mmtcs mmtlr
36 ds245f4 cs8420 10.4 data flow control (03h) the data flow control register configures the fl ow of audio data to/fro m the following blocks: serial audio input port, serial audio output port, aes3 receiver, aes3 transm itter, and sample rate converter. in conjunction with the clock so urce control register, mu ltiple receiver/trans- mitter/transceiver modes may be selected. the out put data should be muted prior to changing bits in this register to avoid transients. amll auto mutes the src data sink when receiver lock is lost, zero data is transmitted. the src data sink may be either, or both, the trans mitter and the serial audio output port. 0 - disables auto mute on loss of lock (default) 1 - enables auto mu te on loss of lock txoff aes3 transmitter output driver control 0 - aes3 transmitter output pin dr ivers normal operation (default) 1 - aes3 transmitter output pin drivers drive to 0 v. aesbp aes3 bypass mode selection 0 - normal operation 1 - connect the aes3 transmitter dr iver input directly to the r xp pin, which become a normal ttl threshold digital input. txd[1:0] aes3 transmitter data source 00 - src output (default) 01 - serial audio input port 10 - aes3 receiver 11 - reserved spd[1:0] serial audio outp ut port data source 00 - src output (default) 01 - serial audio input port 10 - aes3 receiver 11 - reserved srcd input data source for src 0 - serial audio input port (default) 1 - aes3 receiver 7 6 543210 amll txoff aesbp txd1 txd0 spd1 spd0 srcd
ds245f4 37 cs8420 10.5 clock source control (04h) this register configures the clock sources of va rious blocks. in conjunction with the data flow control register, various receiver/transmitter/transceiver modes may be selected. run the run bit controls the internal clocks, allowing the cs8420 to be placed in a ?powered down?, low current consumption, state. 0 - internal clocks are stopped. internal st ate machines are reset. the fully static control port is operational, allowing registers to be read or changed. reading and writing the u and c data buffers is not po ssible. power consumption is low (default). 1 - normal part operation. this bit must be written to the 1 state to allow the cs8420 to begin operation. all inpu t clocks should be stable in frequency and phase when run is set to 1. clk[1:0] output side master clock in put (omck) frequency to output sample rate (fso) ratio selector. if these bits are changed during normal operation, then always stop the cs8420 first (run = 0), then write the new value, then start the cs8420 (run = 1). 00 - omck frequency is 256*fso(default) 01 - omck frequency is 384*fso 10 - omck frequency is 512*fso 11 - reserved outc output time base 0 - omck input pin (modified by the se lected divide ratio bits clk1 & clk0, (default) 1 - recovered input clock inc input time base clock source 0 - recovered input clock (default) 1 - omck input pin (modified by the se lected divide ratio bits clk1 & clk0) rxd[1:0] recovered input clock source 00 - 256*fsi, where fsi is derived from the ilrck pin (only possible when the serial audio input port is in slave mode, default) 01 - 256*fsi, where fsi is derived from the aes3 input frame rate 10 - bypass the pll and apply an external 256*fsi cloc k via the rmck pin. the aes3 receiver is held in synchr onous reset. this setting is useful to prevent unlock interrupts when using an external rmck and inputting data via the serial audio input port. 11 - reserved 7 6 543210 0 run clk1 clk0 outc inc rxd1 rxd0
38 ds245f4 cs8420 10.6 serial audio input po rt data format (05h) sims master/slave mode selector 0 - serial audio input port is in slave mode (default) 1 - serial audio input port is in master mode sisf isclk frequency (for master mode) 0 - 64*fsi (default) 1 - 128*fsi sires[1:0] resolution of the input data, for right-justified formats 00 - 24 bit resolution (default) 01 - 20 bit resolution 10 - 16 bit resolution 11 - reserved sijust justification of sdin data relative to ilrck 0 - left-justified (default) 1 - right-justified sidel delay of sdin data relative to ilrck, for left-justified data formats 0 - msb of sdin data occurs in the first isclk period after the ilrck edge (default) 1 - msb of sdin data occurs in the second isclk period after the ilrck edge sispol isclk clock polarity 0 - sdin sampled on rising edges of isclk (default) 1 - sdin sampled on falling edges of isclk silrpol ilrck clock polarity 0 - sdin data is for the left chann el when ilrck is high (default) 1 - sdin data is for the right channel when ilrck is high 7 6 543210 sims sisf sires1 sires0 sijust sidel sispol silrpol
ds245f4 39 cs8420 10.7 serial audio output po rt data format (06h) soms master/slave mode selector 0 - serial audio output port is in slave mode (default) 1 - serial audio output port is in master mode sosf osclk frequency (for master mode) 0 - 64*fso (default) 1 - 128*fso sores[1:0] resolution of th e output data on sdout and aes3 output when the sa mple rate co nverter is set as the source 00 - 24 bit resolution (default) 01 - 20 bit resolution 10 - 16 bit resolution 11 - direct copy of the received nrz data from the aes3 receiver (including c, u, and v bits, the time slot normally occupied by th e p bit is used to indicate the location of the block start, sdout pin only, serial audio output port clock must be derived from the aes3 receiv er recovered clock) sojust justification of sdou t data relative to olrck 0 - left-justified (default) 1 - right-justified (master mode only) sodel delay of sdout data relative to olrck, for left-justified data formats 0 - msb of sdout data occurs in the first osclk period after the olrck edge (default) 1 - msb of sdout data occurs in the second osclk period after the olrck edge sospol osclk clock polarity 0 - sdout transitions occur on falling edges of osclk (default) 1 - sdout transitions occur on rising edges of osclk solrpol olrck clock polarity 0 - sdout data is for the left c hannel when olrck is high (default) 1 - sdout data is for the right channel when olrck is high 7 6 543210 soms sosf sores1 sores0 so just sodel sospol solrpol
40 ds245f4 cs8420 10.8 interrupt 1 register status (07h) (read only) for all bits in this register, a ?1? means the asso ciated interrupt condition has occurred at least once since the register was last read. a?0? me ans the associated interrupt condition has not occurred since the last reading of the register. r eading the register resets all bits to 0, unless the interrupt mode is set to level and the inte rrupt source is still true. st atus bits that are masked off in the associated mask register w ill always be ?0? in this register . this register defaults to 00. tslip aes3 transmitter source data slip interrupt. in data flows with no src, and where omck, which clocks the aes3 transmitter, is a synchronous to the data source, this bit will go high every time a data sample is dropped or repeated. also, when tcbl is an input, and when the src is not in use, this bit will go high on receipt of a new tcbl signal. oslip serial audio output port data s lip interrupt. when the serial audio output port is in slave mode, and olrck is asynchronous to th e port data source, this bit will go high every time a data sam- ple is dropped or repeated. also, when the src is used, and the src output goes to the output serial port configured in slave mode, this bit will indicate if the ratio of omck frequency to ol- rck frequency does not match what is set in the clk1 and clk0 bits. sre sample rate range exceeded indicator. occurs if fsi/fso or fso/fsi exceeds 3. ovrgl over-range indicator for left (a) channel src output. occurs on intern al over-range for left channel data. note that the cs8420 automatically clips over-ranges to plus or minus full scale. ovrgr over-range indicator for right (b) channel sr c output. occurs on internal over-range for right channel data. note that the cs8420 automatically clips over-ranges to plus or minus full scale detc d to e c-buffer transfer interrupt. the source for this bit is true during the d to e buffer transfer in the c bit buffer management process. eftc e to f c-buffer transfer interrupt. the source for this bit is true during the e to f buffer transfer in the c bit buffer management process. rerr a receiver error has occurred. the receiver error register may be read to determine the nature of the error which caused the interrupt. 7 6 543210 tslip oslip sre ovrgl ovrgr detc eftc rerr
ds245f4 41 cs8420 10.9 interrupt register 2 status (08h) (read only) for all bits in this register, a ?1? means the asso ciated interrupt condition has occurred at least once since the register was last read. a?0? me ans the associated interrupt condition has not occurred since the last reading of the register. re ading the register resets all bits to 0, unless the interrupt mode is set to level and the interrup t source is still true. stat us bits that are masked off in the associated mask regist er will always be ?0? in this regist er. this register defaults to 00. vfifo varispeed fifo overflow indica tor. occurs if the data buffer in the src overflows. this will oc- cur if the input sample rate slows too fast. reunlock sample rate converter unlock indicator. this in terrupt occurs if the src is still tracking a chang- ing input or output sample rate. detu d to e u-buffer transfer interrupt. the source of this bit is true during the d to e buffer transfer in the u bit buffer management process (block mode only). eftu e to f u-buffer transfer interrupt. the source of this bit is true during the e to f buffer transfer in the u bit buffer management process (block mode only). qch a new block of q-subcode data is available fo r reading. the data must be completely read with- in 588 aes3 frames after the interrupt occurs to avoid corruption of the data by the next block. uovw u-bit fifo overwrite. th is interrupt occurs on an overwrite in the u-bit fifo. 10.10 interrupt 1 re gister mask (09h) the bits of this register serve as a mask for the interrupt 1 register. if a mask bit is set to 1, the error is considered unmasked, meaning that its occurrence will affect the int pin and the status r egister. if a mask bit is set to 0, the error is consid ered masked, meaning that its occurren ce will not affect the int pin or the status register. the bit positions ali gn with the corresponding bits in inte rrupt register 1. this register de- faults to 00. 10.11 interrupt register 1 mode registers msb & lsb (0ah,0bh) the two interrupt mode registers form a 2-bit code for ea ch interrupt register 1 f unction. this code deter- mines whether the int pin is set active on the arrival of the interrupt condition, on the removal of the interrupt condition, or on the continuing occurrence of the interrupt condition. these registers default to 00. 00 - rising edge active 01 - falling edge active 10 - level active 11 - reserved 7 6 543210 0 0 vfifo reunlock detu eftu qch uovw 7 6 543210 tslipm oslipm srem ovrglm ovrgrm detcm eftcm rerrm 7 6 543210 tslip1 oslip1 sre1 ovrgl1 ovrgr1 detc1 eftc1 rerr1 tslip0 oslip0 sre0 ovrgl0 ovrgr0 detc0 eftc0 rerr0
42 ds245f4 cs8420 10.12 interrupt 2 register mask (0ch) the bits of this register serve as a mask for the interrupt 2 register. if a mask bit is set to 1, the error is considered unmasked, meaning that it s occurrence will affect the int pin and the status register. if a mask bit is set to 0, the error is consid ered masked, meaning that its occurrence will not a ffect the int pin or the status register. the bit positions alig n with the corresponding bits in inte rrupt register 2. this register de- faults to 00. 10.13 interrupt register 2 mode registers msb & lsb (0dh,0eh) the two interrupt mode registers form a 2-bit code for each interrupt 2 register function. this code deter- mines whether the int pin is set active on the arrival of the interrupt condition, on the removal of the interrupt condition, or on the continuing occurrence of the interrupt condition. these registers default to 00. 00 - rising edge active 01 - falling edge active 10 - level active 11 - reserved 76543210 0 0 vfifom reunlockm detum eftum qchm uovwm 76543210 0 0 vfifo1 reunlock1 de tu1 eftu1 qch1 uovw1 0 0 vfifo0 reunlock0 de tu0 eftu0 qch0 uovw0
ds245f4 43 cs8420 10.14 receiver channel stat us (0fh) (read only) the bits in this register can be associated with either channel a or b of the received data. the desired channel is selected with the chs bit of the channel status data buffer control regis- ter. aux[3:0] the aux3-0 bits indicate th e width of the incoming auxiliary data field, as indicated by the in- coming channel status bits, decoded according to iec60958 and aes3. 0000 - auxiliary da ta is not present 0001 - auxiliary data is 1 bit long 0010 - auxiliary data is 2 bits long 0011 - auxiliary data is 3 bits long 0100 - auxiliary data is 4 bits long 0101 - auxiliary data is 5 bits long 0110 - auxiliary data is 6 bits long 0111 - auxiliary data is 7 bits long 1000 - auxiliary data is 8 bits long 1001 - 1111 reserved pro channel status block format indicator 0 - received channel status block is in consumer format 1 - received channel status block is in professional format audio audio indicator 0 - received data is linearly coded pcm audio 1 - received data is not linearly coded pcm audio copy scms copyright indicator 0 - copyright asserted 1 - copyright not asserted orig scms generation indicator. this is decoded from the category code and the l bit. 0 - received data is 1st generation or higher 1 - received data is original note: copy and orig will both be set to 1 if the incoming data is flagged as profes sional or if the receiver is not in use. 76543210 aux3 aux2 aux1 aux0 pro audio copy orig
44 ds245f4 cs8420 10.15 receiver error (10h) (read only) this register contains the aes3 receiver and pll status bits . unmasked bits will go high on occurrence of the error, and will stay high until the register is re ad. reading the register resets all bits to 0, unless the error source is still true. bits that ar e masked off in t he receiver error mask register will always be 0 in this re gister. this register defaults to 00. qcrc q-subcode data crc error has occurred. updated on q-subcode block boundaries. 0 - no error 1 - error ccrc channel status block cyclic redundancy check bit. updated on cs block boundaries. this bit is valid in professional mode only. 0 - no error 1 - error unlock pll lock status bit. updated on cs block boundaries. 0 - pll locked 1 - pll out of lock v received aes3 validity bit status. updated on sub-frame boundaries. 0 - data is valid and is normally linear coded pcm audio 1 - data is invalid, or may be valid compressed audio conf confidence bit. updated on sub-frame boundaries. 0 - no error 1 - confidence error. this in dicates that the received data eye opening is less than half a bit period, indicating a poor lin k that is not meeting specifications. bip bi-phase error bit. updated on sub-frame boundaries. 0 - no error 1 - bi-phase error. this indicates an error in the received bi-phase coding. par parity bit. updated on sub-frame boundaries. 0 - no error 1 - parity error 76543210 0 qcrc ccrc unlock v conf bip par
ds245f4 45 cs8420 10.16 receiver error mask (11h) the bits in this register serve as masks for th e corresponding bits of the receiver error regis- ter. if a mask bit is set to 1, the error is cons idered unmasked, meaning that its occurrence will appear in the receiv er error register, will affect the rerr pin, will affect th e rerr interrupt, and will affect the current audio sample according to the status of t he hold bit. if a mask bit is set to 0, the error is considered masked, meaning that it s occurrence will not ap pear in the receiver error register, will not affe ct the rerr pin, will not affect the rerr inte rrupt, and will not affect the current audio sample. the ccrc and qcrc bits behave differently from the other bits: they do not affect the curr ent audio sample even when unmasked. this register defaults to 00. 10.17 channel status data buffer control (12h) bsel selects the data buffer regist er addresses to contain user data or channel status data 0 - data buffer address space contai ns channel status data (default) 1 - data buffer address space contains user data cbmr control for the first 5 byte s of channel status ?e? buffer 0 - allow d to e buffer transfers to overwr ite the first 5 bytes of channel status data (default) 1 - prevent d to e buffer transfers from over writing first 5 bytes of channel status data detci d to e c-data buffer transfer inhibit bit. 0 - allow c-data d to e buffer transfers (default) 1 - inhibit c-data d to e buffer transfers eftci e to f c-data buffer transfer inhibit bit. 0 - allow c-data e to f buffer transfers (default) 1 - inhibit c-data e to f buffer transfers cam c-data buffer control port access mode bit 0 - one byte mode 1 - two byte mode chs channel select bit 0 - channel a information is displayed at the emph pin and in the receiver channel status register. channel a information is output during control port reads when cam is set to 0 (one byte mode) 1 - channel b information is displayed at the emph pin and in the receiver channel status register. channel b information is output during control port reads when cam is set to 0 (one byte mode) 76543210 0 qcrcm ccrcm unlockm vm confm bipm parm 76543210 0 0 bsel cbmr detci eftci cam chs
46 ds245f4 cs8420 10.18 user data buffer control (13h) ud user data pin (u) direction specifier 0 - the u pin is an input. th e u data is latched in on both rising and falling edges of olrck. this setting also chooses the u pin as the source for transmitted u data (default). 1 - the u pin is an output. the received u data is clocked out on both rising and falling edges of ilrck. this setting also chooses the u data buffer as the so urce of transmitted u data. ubm[1:0] sets th e operating mode of the aes3 u bit manager 00 - transmit all zeros mode (default) 01 - block mode 10 - reserved 11 - iec consumer mode b detui d to e u-data buffer transfer inhibit bit (va lid in block mode only). 0 - allow u-data d to e buffer transfers (default) 1 - inhibit u-data d to e buffer transfers eftui e to f u-data buffer transfer inhibit bit (valid in block mode only). 0 - allow u-data e to f buffer transfers (default) 1 - inhibit u-data e to f buffer transfer q-channel subcode bytes 0 to 9 (14h - 1dh) (read only) the following 10 registers contain the decoded q-channel subcode data each byte is lsb first with respect to the 80 q-subcode bits q[79:0]. thus bit 7 of address 14h is q[0] while bit 0 of address 14h is q[7]. similarly bit 0 of address 1dh corresponds to q[79]. 76543210 0 0 0 ud ubm1 ubm0 detui eftui 76543210 control control control contr ol address address address address track track track track track track track track index index index index index index index index minute minute minute minute m inute minute minute minute second second second second second second second second frame frame frame frame frame frame frame frame zero zero zero zero zero zero zero zero abs minute abs minute abs minute abs minute ab s minute abs minute abs minute abs minute abs second abs second abs second abs second abs second abs second abs second abs second abs frame abs frame abs frame abs frame abs frame abs frame abs frame abs frame
ds245f4 47 cs8420 10.19 sample rate ratio (1eh) (read only) the sample rate ratio is fso divided by fsi. this value is represented as an integer and a fractional part. the value is meaningful only after the both the pll and src have reached lock, and the src output is being used srr[7:6 the integer part of the sample rate ratio srr[5:0] the fractional part of the sample rate ratio 10.20 c-bit or u- bit data buffer (20h - 37h) either channel status data buffer e or user data buffer e (provided ubm bits are set to block mode) is ac- cessible via these register addresses. 10.21 cs8420 i.d. and version register (7fh) (read only) id[3:0] id code for the cs8420. permanently set to 0001 ver[3:0] cs8420 revision level: revision b is coded as 0001 revision c is coded as 0011 revision d is coded as 0100 76543210 srr7 srr6 srr5 srr4 srr3 srr2 srr1 srr0 7654321id3 id3 id2 id1 id0 ver3 ver2 ver1 ver0
48 ds245f4 cs8420 11. system and applications issues 11.1 reset, power down and start-up options when rst is low, the cs8420 enters a low-power mode. all internal states are reset, including the control port and registers, and the outputs are muted. when rst is high, the control port becomes operational, and the desired settings should be loaded into the control registers. writ ing a 1 to the run bit will then cause the part to leave the low- power state and beg in operation. after the pll and the src have settled, the aes3 and serial audio ou tputs will be enabled. some options within the cs8420 are controlled by a st art-up mechanism. during the reset state, some of the output pins are reconfigured internally to be inpu ts. immediately upon exiting the reset state, the level of these pins is sensed. the pins ar e then switched to be outputs. this mechanism allows output pins to be used to set alternative modes in the cs8420 by connecting a 47 k resistor between the pin and either vd+ (high) or dgnd (low). for each mode, every start-up option select pin must have an external pull-up or pull-down resistor. in software mode, the only start-up option pin is emph , which is used to set a chip ad- dress bit for the control port in i2c mode. hardware modes use many start-up options, which are detailed in the hardware definition section at the end of this data sheet. 11.2 transmitter startup when the cs8420 is taken out of power-down and the aes3 receiver is configured to be in-circuit, the part uses the clock recovered from the aes3 input stream to advance its internal state machine to run. this can be a problem if no valid aes3 stream is present at the rxp/rxn pins and data input through the serial audio port needs to be output through the aes3 transmitter. to complete initialization and begin operation when th e aes3 receiver is in-circu it and no valid aes3 input stream is presented to the rxp/rxn pins, th e user must execute the following sequence: 1. place the cs8420 in power-down (run = 0). 2. set the serial audio input and output ports to slave mode (sims = 0, soms = 0). 3. set the input and output time base to the omck input pin (outc = 0, inc = 1). 4. configure the src to receiv e its input from the serial audio input port (srcd = 0). 5. configure the serial audio output port to receive its input from the serial audio input port (spd[1:0] = 01). 6. configure the aes3 transm itter to receive its inpu t from the serial audio input port (t xd[1:0] = 01). 7. set the run bit (run = 1). after completing steps 1-7, the tran smitter will function properl y, and the data flow can be altered for the application without powering down.
ds245f4 49 cs8420 11.3 src invalid state occasionally the cs8420 src will enter an invalid state. this can happ en after the run bit has been set when an aes3 stream is firs t plugged into the part or when a source device interr upts the src input stream. when this happens, two symptoms may be noticeable: notches occurring in the frequency response and spurious tones being generated in response to some input frequencies. to avoid this problem in software mode, use the micr ocontroller to monitor the unlock bit in control reg- ister 10h. when the part achieves lock, clear the run bit in register 4 and then set it again. this will reset all internal state machines. alternately, the user may use the following sequence: 1. power on cs8420. 2. write the following register sequence: 3. wait for pll to lock. 4. wait 250ms for src to lock. 5. write the following register sequence: 6. if pll goes out of lock, start at step 2 and repeat. when synchronizing multiple cs8420s, wait for all plls to lock before continuing to the next step. these actions clear the invalid state if it has occurred. in hardware mode, monitor the rerr pin for receiver lock status. when the part achieves lock, set the rst pin low for at least 200 s and then set it high again. this action clears the invalid state if it has occurred. when polling the rerr pin again, the user must account for the fact t hat the rerr pin will be high during reset and remain high until the pll has reachieved lock. in either software or hardware mode, when clearing the invalid state, it is ad visable to mute any devices connected to the output of the cs8420. 11.4 c/u buffer data corruption occasionally the c/u buffer data may be corrupted. this can happen after the run bit has been set and data has been written to the c/u buffer (20h-37h). if no further data is writte n to the c buffer after the initial write and the receiver input is interrupted multiple times, the contents of the buffer may be reset to all zeros. the buffer will not be corrupted if the buffer data is being updated, on ly when the data is static and the re- ceiver input has been interrupted multiple times. to avoid this problem in software mode when the c/ u buffer contents should remain static, use the micro- controller to monitor the unlock bit in control register 10h or the rerr pin. if the part indicates the pll has lost lock, rewrite the c/u buffer data. repeat th is action every time the pll goes out of lock. in hardware mode, this limitation does not exist as the serial c/u da ta is being fed directly to the transmitter. register value 04h 09h 03h 95h 04h 49h register value 03h 81h 04h 41h
50 ds245f4 cs8420 11.5 block-mode u-data d- to-e buffer transfers when fsi fso, block-mode u-data transfers from the d buffer to the e buffer are not synchronous to the input clock domain. d-to-e buffer tran sfers can always be detected by the activation of the detu bit (bit 3 in register 08h) when fsi fso or fsi = fso. iec consumer b mode, serial u-data output, and the q- channel subcode bytes (registers 14h - 1dh) are una ffected by the input/output sample rate relationship. 11.6 id code and revision code the cs8420 has a register that cont ains a 4-bit code to indicate that the addressed device is a cs8420. this is useful when other cs84xx family members are resident in th e same system, a llowing common soft- ware modules. the cs8420 4-bit revision code is also available. this allows the software driver for the cs8420 to identify which revision of the device is in a particular system , and modify its behavior accordingly. to allow for future revisions, it is strongly recommend that the revision code is read into a variable area within the microcon- troller, and used wherever appropriate as revision details become known. 11.7 power supply, gr ounding, and pcb layout for most applications, the cs8420 can be operated from a single +5v supply, following normal supply de- coupling practice (see figure 5. ?recommended connection diagram for software mode? on page 12 ). for applications where the recovered input clock, output on the rmck pin, is required to be low-jitter, then use a separate, quiet, analog +5v supply for va+, decoupled to agnd. in addition, a separate region of analog ground plane around the filt, agnd, va+, rxp and rxn pins is recommended. the vd+ supply should be well-decoupled with a 0.1 f capacitor to dgnd to minimize aes3 transmitter induced transients. extensive use of power and ground planes, ground plane fill in un used areas and surf ace mount decoupling capacitors are recommended. make sure decoupling capacitors are mounted on the same side of the board as the cs8420, to minimize via inductance effects. all decoupling capacitors should be as close to the cs8420 as possible. 11.8 synchronization of multiple cs8420s the serial audio output ports of multiple cs8420s ca n be synchronized by sharin g the same master clock, osclk, olrck, and rst line and ensuring that all devices leave the reset state on the same master clock falling edge. either all the port s need to be in slave mode, or one can be set as a master. the aes3 transmitters may be synch ronized by sharing the same master clock, tcbl, and rst signals, and ensuring all devices leave the reset state on the sa me master clock falling edge. the tcbl pin is used to synchronize multiple cs8420 aes3 transmitters at the channel st atus block boundar ies. one cs8420 must have its tcbl set to master; the others must be set to slave tcbl. alternatively, tcbl can be derived from some external logic, in which case all the cs8420 devices should be set to slave tcbl. 11.9 extended range sample rate conversion for handling sampling rate conversion ratios greater th an 3:1 or less than 1:3, the user can use a cascade of two devices. the product of the conversion ratio of the two devices should eq ual the target conversion ratio.
ds245f4 51 cs8420 12. software mode - pin description the above diagram and the following pi n descriptions apply to software mode. in hardware mode, some pins change their function as described in subsequent sections of this data sheet. fixed function pins are marked with a *, and will be described once in this se ction. pins marked with a + are used upon reset to select various start-up options, and require a pull-up or pull-down resistor. power supply connections: vd+ - positive digital power * positive supply for the digi tal section. nominally +5.0 v. va+ - positive analog power * positive supply for the analog section. nominally +5.0 v. this supply should be as quiet as possible since noise on this pin will directly affe ct the jitter performance of the recovered clock. dgnd - digital ground * ground for the digital section. dgnd should be connected to the same ground as agnd. agnd - analog ground * ground for the analog section. agnd should be connected to the same ground as dgnd. clock-related pins: omck - output section master clock input output section master clock input. the frequency must be 256x, 384x, or 512x the output sample rate (fso). rmck - input section recove red master clock output input section recove red master clock ou tput. will be at a frequency of 128x or 256x the input sample rate (fsi).
52 ds245f4 cs8420 filt - pll loop filter * an rc network should be connected between this pi n and ground. recommended schematic and component val- ues are given in ?pll filter? on page 87 . overall device control: h/s - hardware or software control mode select * the h/s pin determines the method of controlling the operat ion of the cs84 20, and the method of accessing cs and u data. in software mode, device control and cs and u data access is primarily via the control port, using a microcontroller. in hardware mode, alternate modes and ac cess to cs and u data is provided by pins. this pin should be permanently tied to vd+ or dgnd. rst - reset input * when rst is low, the cs8420 enters a low-po wer mode and all internal states are reset. on initial power-up, rst must be held low until the power supply is stable, and a ll input clocks are stable in frequency and phase. this is particularly true in hardware mode wi th multiple cs8420 devices, where synchronization between devices is impor- tant. int - interrupt output the int output pin indicates errors and key events during the operation of the cs8420 . all bits affecting int are maskable via control registers. the condition(s) that initiate d interrupt are readable via a control register. the polarity of the int output, as well as selection of a standard or open -drain output, is set via a control register. once set true, the int pin goes false only after the interrupt status registers have been read, and the interrupt status bits have re- turned to zero. audio input interface: sdin - serial audio input port data input audio data serial input pin. isclk - serial audio input port bit clock input or output serial bit clock for audio data on the sdin pin. ilrck - serial audio input port left/right clock input or output word rate clock for the audio data on the sdin pin. the frequency will be at the input sample rate (fsi) aes3/spdif receiver interface: rxp, rxn - differential line receiver inputs differential line rece iver inputs, carryi ng aes3-typ e data. rerr - receiver error indicator when high, indicates a problem with the operation of the aes3 receiver. the status of this pin is updated once per sub-frame of in coming aes3 data. conditions that can cause rerr to go high are: validity, pa rity error, bi-phase coding error, confidence, qcrc and ccrc errors, as well as loss of lock in the pll. op tionally, each condition may be masked from affecting the rerr pin using the receiver error mask register. the rerr pin tracks the status of the unmasked errors: the pin goes high as soon as an unmasked error occurs and goes low immediately when all unmasked errors go away.
ds245f4 53 cs8420 emph - pre-emphasis indicator output emph is low when the inco ming aes3 data indicates the presence of 50/15 s pre-emphasis. when the aes3 data indicates the absence of pre-emphasis or the presence of other than 50/15 s pre-emphasis emph is high. this is also a start-up option pin, and requires a 47 k resistor to either vd+ or dgnd, which determines the ad2 address bit for the control port in i2c mode. audio output interface: sdout - serial audio output port data output audio data serial output pin. osclk - serial audio output port bit clock input or output serial bit clock for audio data on the sdout pin. olrck - serial audio output port left/right clock input or output word rate clock for the audio data on the sdout pin. the frequency will be at the output sample rate (fso) aes3/spdif transmitter interface: tcbl - transmit channel status block start this pin can be configured as an input or output. when operated as output, tcbl is high during the first sub-frame of a transmitted channel status block, and low at all other times. when operated as input, driving tcbl high for at least three omck (or rmck, depending on which clock is operating the aes3 encoder block) cl ocks will cause the next transmitted sub-frame to be t he start of a channel status block. txn, txp - differential line driver outputs differential line driver outputs, transmitting aes3 type data. drivers are pulled to low while the cs8420 is in the reset state. control port signals: scl/cclk - control port clock scl/cclk is the serial control interfac e clock, and is used to clock control da ta bits into and out of the cs8420. ad0/cs - address bit 0 (i2c) / cont rol port chip select (spi) a falling edge on this pin puts the cs8 420 into spi control port mode. with no falling edge, the cs8420 defaults to i2c mode. in i2c mode, ad0 is a chip address pin. in spi mode, cs is used to enable the control port interface on the cs8420. ad1/cdin - address bit 1 (i2c) / serial control data in (spi) in i2c mode, ad1 is a chip address pin. in spi mode, cd in is the input data line for the control port interface sda/cdout - serial c ontrol data i/o (i2c) / data out (spi) in i2c mode, sda is the control i/o data line. sda is open drain and requires an external pull-up resistor to vd+. in spi mode, cdout is the output data from the control port interface on the cs8420.
54 ds245f4 cs8420 miscellaneous pins: u - user data the u pin may optionally be used to input user data fo r transmission by th e aes3 transmitter (see figure 20 for timing information). altern atively, the u pin may be set to output user data from the aes3 receiver (see figure 19 for timing information). if not driven, a 47 k pull-down resistor is recommended fo r the u pin since the default state of the ud direction bit sets the u pin as an input. the pull-down resistor ensures that the transmitted user data will be zero. if the u pin is always set to be an output, thereby causing the u bit manager to be the source of the u data, the resistor is not necessary. the u pin should not be tied di rectly to ground in case it is programmed to be an output and subsequently tries to output a logic high. this situat ion may affect the long-term re liability of the device. if the u pin is driven by a logic level output, a 100 series resistor is recommended.
ds245f4 55 cs8420 13. hardware modes 13.1 overall description the cs8420 has six hardware modes, which allow use of the device without using a micro-controller to ac- cess the device control registers and cs & u data. th e flexibility of the cs8420 is necessarily limited in hardware mode. various pins change function in hard ware mode, and various data paths are also possible. these alternatives are identified by hardware mode numbers 1 through 6. the following sections describe the data flows and pin definitions for each hardware mode. 13.1.1 hardware mode definitions hardware mode is selected by connecting the h/s pin to ?1?. in hardware mode, 3 pins (dfc0, dfc1 & s/aes ) determine the hardware mode number, according to ta b l e 5 . start-up options are used exten- sively in hardware mode. options include whether the serial audio output ports are master or slave, the serial audio ports? format and whether tcbl is an input or an output. which output pins are used to set which modes depends on which hardware mode is being used. 13.1.2 serial audio port formats in hardware mode, only a limited number of alternativ e serial audio port formats are available. these for- mats are described by tables 6 and 7 , which define the equivalent software mode bit settings for each format. timing diagrams are shown in figures 17 and 18 . for each hardware mode, the following pages contain a data flow diagram, a pin-out drawing, a pin de- scriptions list and a definition of the available start-up options. dfc1 dfc0 s/aes hardware mode number 0 0 0 1 - default data flow, aes3 input 0 0 1 2 - default data flow, serial input 0 1 - 3 - transceive flow, with src 1 0 - 4 - transceive flow, no src 1 1 0 5 - aes3 rx only, aes3 input 1 1 1 6 - aes3 tx only, serial input table 5. hardware mode definitions sosf sores1/0 sojust sodel sospol solrpol of1 - left-justified 0 00 0 0 1 0 of2 - i2s 24-bit data 0 00 0 1 0 1 of3 - right-justified, master mode only 000 1 0 0 0 of4 - i2s 16-bit data 0 10 0 1 0 1 of5 - direct aes3 data 0 11 0 0 1 0 table 6. serial audio output formats available in hardware mode sisf sires1/0 sijust sidel sispol silrpol if1 - left-justified 0 00 0 0 1 0 if2 - i2s 0 00 0 1 0 1 if3 - right-justified 24-bit data 0 00 1 0 0 0 if4 - right-justified 16-bit data 0 10 1 0 0 0 table 7. serial audio input formats available in hardware mode
56 ds245f4 cs8420 13.2 hardware mode 1 description (default data flow, aes3 input) hardware mode 1 data flow is shown in figure 24 . audio data is input via th e aes3 receiver, and rate con- verted. the audio data at the new rate is then output both via the serial audio output port and via the aes3 transmitter. the channel status data, user data and validity bit information are handled in four alternative modes: 1a and 1b, determined by a start-up resistor on the copy pi n. in mode 1a, the received pro, copy, orig, em- ph , and audio channel status bits are output on pins. the transmitted channel status bits are copied from the received channel status data, and the transmitted u and v bits are 0. in mode 1b, only the copy and orig pins are output , and reflect the received channel status data. the transmitted channel status bits, user data and valid ity bits are input seria lly via the pro/c, emph /u and audio /v pins. figure 20 shows the timing requirements. start-up options are shown in ta b l e 8 , and allow choice of the serial audio output port as a master or slave, choice of four serial audio output port formats, and the source for transmitted c, u and v data. the following pages contain the detailed pin descriptions for hardware mode 1. if a validity, parity, bi-phase, or lock receiver er ror occurs, the current au dio sample will be held. sdout rmck rerr copy function lo - - - serial output port is slave hi - - - serial output port is master - - - lo mode1a: c transmitted data is copied from received data, u & v = 0, received pro, emph , audio are visible. - - - hi mode 1b: cuv transmitted data is input serially on pins, received pro, emph , audio are not visible - lo lo serial output format of1 - lo hi serial output format of2 - hi lo serial output format of3 - hi hi serial output format of4 table 8. hardware mode 1 start-up options aes3 encoder &tx serial audio output aes3 rx & decoder sample rate converter c&ubitdatabuffer clocked by output clock clocked by input derived clock rxp rxn olrck osclk sdou t txp txn rmck rerr copy orig emph/u tcbld pro/c audio/v tcbl mute dfc0 dfc1 s/aes vd+ h/s o utput clock source omck power supply pins (vd+, va+, dgnd, agnd), the reset pin (rst) and the pll filter pin (filt) are omitted from this dia g ram. please refer to the t y pical connection dia g ram for hook-up details. figure 24. hardware mode 1 - default data fl ow, aes3 input
ds245f4 57 cs8420 13.2.1 pin description - hardware mode 1 overall device control: dfc0, dfc1 - data flow control inputs dfc0 and dfc1 inputs determine the major data flow op tions available in hardware mode, as shown in table 5 . s/aes - serial audio or aes3 input select s/aes is connected to ground in hardware mode 1 in order to select the aes3 input. mute - mute output data input if mute is low, audio data is passed normally. if mute is high, both the aes3 transmitted audio data and the serial audio output port data is set to digital zero. omck - output section master clock input output section master clock input. the frequency must be 256x the output sample rate (fso). aes3/spdif receiver interface: rxp, rxn - differential line receiver inputs differential line receiver i nputs, carrying aes3 type data. rmck - input section recove red master clock output input section recovered ma ster clock output. will be at a fr equency of 256x the input sample rate (f si). this is also a start-up option pin and requires a pull-up or pull-down resistor.
58 ds245f4 cs8420 rerr - receiver error indicator when high, indicates a problem with the operation of the aes3 receiver. the status of this pin is updated once per sub-frame of incoming aes3 data. conditions that cause rerr to go high are: parity error, and bi-phase coding error, as well as loss of lock in the pll. this is also a start-up option pin, and requires a pull-up or pull-down resistor. emph /u - pre-emphasis indicator output or u-bit data input the emph /u pin reflects either the state of the emph channel status bits in the in coming aes3 type data stream, or is the serial u-bit input for the aes3 type transm itted data, clocked by olrck. when indicating emphasis, emph /u is low if the incoming data indicates 50/15 s pre-emphasis and high otherwise. copy - copy channel status bit output the copy pin reflects the state of the copy channel status bit in the incoming aes3 type data stream. this is also a start-up option pin, and requires a pull-up or pull-down resistor. orig - original channel status output scms generation indicator. this is decoded from the inco ming category code and the l bit. a low output indicates that the audio data stream is 1st generation or higher. a high indicates that the audio data stream is original. pro/c - professional channel status bit output or c-bit data input the pro/c pin either reflects the state of the professio nal/consumer channel status bi t in the incoming aes3 type data stream, or is the serial c-bit input for the aes3 type transmitted data, clocked by olrck. audio /v - audio channel status bit output or v-bit data input the audio /v pin either reflects the state of the audio/non audio chan nel status bit in the incoming aes3 type data stream, or is the v-bit data in put for the aes3 type transmitted data stream, clocked by olrck. audio output interface: sdout - serial audio output port data output audio data serial output pin. this is also a start-up option pin, and requires a pull-up or pull-down resistor. osclk - serial audio output port bit clock input or output serial bit clock for audio data on the sdout pin. olrck - serial audio output port left/right clock input or output word rate clock for the audio data on the sdout pin. the fr equency will be at the output sample rate (fso) aes3/spdif transmitter interface: tcbl - transmit channel status block start when operated as output, tcbl is high during the first su b-frame of a transmitted channel status block, and low at all other times. when o perated as input, driving tcbl high for at least three omck clocks will cause the current transmitted sub-frame to be the start of a channel status block. tcbld - transmit channel status block direction input connect tcbld to vd+ to set tcbl as an output. connect tcbld to dgnd to set tcbl as an input. txn, txp - differential line driver outputs differential line driver output s, transmitting aes3 type data. drivers are pulled to low wh ile the cs8420 is in the reset state.
ds245f4 59 cs8420 13.3 hardware mode 2 description (default data flow, serial input) hardware mode 2 data flow is shown in figure 25 . audio data is input via the serial audio input port, and rate converted. the audio data at the new rate is then output both via t he serial audio output port and via the aes3 transmitter. the c, u, and v bits in the aes3 output stream may be set in two methods, selected by the cuven pin. when cuven is low, mode 2a is se lected, where copy/c, orig/u, and emph /v pins allow selected channel status data bits to be set. the copy and orig pins are used to set the pro bit, the copy bit, and the l bit, as shown in ta b l e 9 . in consumer mode, the transmitted category code shall be 0101100b, which indicates sample rate converter. the transmitted u and v bits are zero.when the cuven pin is high, mode 2b is selected, where copy/c, orig/u, and emph /v become serial bit inputs for c, u, and v data. this data is clocked by both edges of olrc k, and the channel status block start is indicated or determined by tcbl. figure 20 shows the timing requirements. audio serial port data formats are selected as shown in tables 6 , 7 and 10 . start-up options are shown in ta b l e 11 , and allow choice of the serial audio output port as a master or slave and whether tcbl is an input or an output. the serial audio input port is always a slave. aes3 encoder &tx serial audio output serial audio input sample rate converter c&ubitdatabuffer clocked by output clock clocked by input derived clock ilrck isclk olrck osclk sdou t txp txn rmck lock copy/c orig/u emph/v cuven tcbl dfc0 dfc1 s/aes vd+ h/s output clock source omck power supply pins (vd+, va+, dgnd, agnd) & the re set pin (rst) and the pll filter pin (filt) areomittedfromthisdia g ram. please refer to the t y pical connection dia g ram for hook-up details. vd+ sdin sfmt1 sfmt0 figure 25. hardware mode 2 - default data flow, serial audio input
60 ds245f4 cs8420 copy/c orig/u function 00 pro=0, copy=0, l=0 01 pro=0, copy=0, l=1 10 pro=0, copy=1, l=0 11 pro=1 table 9. hw mode 2a copy/c and orig/u pin function sfmt1 sfmt0 function 00 serial input & output format if1&of1 01 serial input & output format if2&of2 10 serial input & output format if3&of3 11 serial input & output format if4&of3 table 10. hw mode 2 serial audio port format selection sdout lock function lo - serial output port is slave hi - serial output port is master - lo tcbl is an input - hi tcbl is an output table 11. hardware mode 2 start-up options
ds245f4 61 cs8420 13.3.1 pin description - hardware mode 2 overall device control: dfc0, dfc1 - data flow control inputs dfc0 and dfc1 inputs determine the major data flow op tions available in hardware mode, according to table 5 . s/aes - serial audio or aes3 input select s/aes is connected to vd+ in hardware mode 2, in order to select the serial audio input. sfmt0, sfmt1 - serial audio port data format select inputs sfmt0 and sfmt1 select the serial audio input and output ports? format. see ta b l e 1 0 . omck - output section master clock input output section master clock input. the frequency must be 256x the output sample rate (fso). audio input interface: sdin - serial audio input port data input audio data serial input pin. isclk - serial audio input port bit clock input or output serial bit clock for audio data on the sdin pin. ilrck - serial audio input port left/right clock input or output word rate clock for the audio data on the sdin pin. the frequency will be at the input sample rate (fsi)
62 ds245f4 cs8420 rmck - input section recovered master clock output input section recover ed master clock output. will be at a frequency of 256x th e input sample rate (fsi). lock - pll lock indicator output lock low indicates that the pll is locked. this is also a start-up option pin, and requires a pull-up or pull-down resistor. audio output interface: sdout - serial audio output port data output audio data serial output pin. this is also a start-up option pin, and requires a pull-up or pull-down resistor. osclk - serial audio output port bit clock input or output serial bit clock for audio data on the sdout pin. olrck - serial audio output port left/right clock input or output word rate clock for the audio data on the sdout pin. the fr equency will be at the output sample rate (fso). aes3/spdif transmitter interface: txn, txp - differential line driver outputs differential line driver output s, transmitting aes3 type data. drivers are pulled to low wh ile the cs8420 is in the reset state. tcbl - transmit channel status block start when operated as output, tcbl is high during the first su b-frame of a transmitted channel status block, and low at all other times. when o perated as input, driving tcbl high for at least three omck clocks will cause the current transmitted sub-frame to be the start of a channel status block. cuven - c, u and v bit input enable mode input the cuven pin determines how the channel status data, user data and validity bit is input. when cuven is low, hardware mode 2a is selected, where the emph /v, copy/c and orig/u pins are used to enter selected channel status data. when cuven is high, hardware 2b is selected, where the emph /v, copy/c and orig/u pins are used to enter serial c, u and v data. emph /v - pre-emphasis indicator input or v bit input in mode 2a, emph /v low sets the 3 emph channel status bits to indicate 50/15 s pre-emphasis. emph /v high sets the 3 emph bits to 000 indicating no pre-emphasis. in mode 2b, emph /v low sets the v bit to indicate valid audio. emph /v high sets the v-bit to indicate non-valid audio. copy/c - copy channel status bit input or c bit input in mode 2a, the copy/c pin determines the state of the copy, pro and l channel status bits in the outgoing aes3 type data stream (see ta b l e 9 ). in mode 2b, copy/c becomes the direct c bit input data pin. orig/u - orig channel status bit input or u bit input in mode 2a, the orig/u pin determines the state of the copy, pro and l ch annel status bits in the outgoing aes3 type data stream. (see ta b l e 9 ). in mode 2b, orig/u becomes the direct u bit input data pin.
ds245f4 63 cs8420 13.4 hardware mode 3 description (transceive data flow, with src) hardware mode 3 data flow is shown in figure 26 . audio data is input via the aes3 receiver, and rate con- verted. the audio data at the new rate is then output via the serial audio output port. different audio data, synchronous to omck, may be input in to the serial audio input port, and output via the aes3 transmitter. the channel status data, user data, and validity bit information are handled in two alternative modes: 3a and 3b, determined by a start-up resistor on the copy pin. in mode 3a, the received pro, copy, orig, and audio channel status bits are output on pins. the tr ansmitted channel status bits are copied from the received channel status data, and the transmitted u and v bits are zero. in mode 3b, only the copy, and orig pins are out put, and reflect the received channel status data. the transmitted channel status bits, user data, and va lidity bits are input seri ally via the pro/c, emph /u, and audio /v pins. figure 20 shows the timing requirements. the serial audio input port is always a slave. if a validity, parity, bi-phase, or lock receiver error occurs, the current audio sample will be held. start-up options are shown in table 12 , and allow choice of the serial audio output port as a master or slave, whether tcbl is an input or an output, the serial audi o ports formats, and the source of the transmitted c, u, and v data. the following pages contain the detailed pin descriptions for hardware mode 3. aes3 encoder &tx serial audio output aes3 rx & decoder sample rate converter c & u bit data buffer clocked by output clock clocked by input derived clock rxp rxn olrck osclk sdout txp tx n rmck rerr copy orig emph/u audio/v tcbl dfc0 dfc1 vd+ h/s o utput clock source omck power supply pins (vd+, va+, dgnd, agnd) & the reset pin (rst) and the pll filter pin (filt) are omitted from this dia g ram. please refer to the t y pical connection dia g ram for hook-up details. vd+ serial audio input ilrck isclk sdin pro/c figure 26. hardware mode 3 - transceive data flow, with src
64 ds245f4 cs8420 sdout rmck rerr orig copy function lo - - - - serial output port is slave hi - - - - serial output port is master - - - - lo mode 3a: c transmitted data is copied from received data, u & v =0, received pro, emph , audio is visible - - - - hi mode 3b: cuv transmitted data is input serially on pins, received pro, emph and audio is not visible - lo lo - - serial input & output format if1&of1 - lo hi - - serial input & output format if2&of2 - hi lo - - serial input & output format if3&of3 - hi hi - - serial input & output format if2&of4 - - - lo - tcbl is an input - - - hi - tcbl is an output table 12. hardware mode 3 start-up options
ds245f4 65 cs8420 13.4.1 pin description - hardware mode 3 overall device control: dfc0, dfc1 - data flow control inputs dfc0 and dfc1 inputs determine the major data flow options available in hardware mode, according to ta b l e 5 . omck - output section master clock input output section master clock input. the frequency must be 256x the output sample rate (fso). audio input interface: sdin - serial audio input port data input audio data serial input pi n. this data will be trans mitted out the aes3 port. isclk - serial audio input port bit clock input serial bit clock for audio data on the sdin pin. ilrck - serial audio input port left/right clock input word rate clock for the audio data on the sdin pin. the frequency will be at the output sample rate (fso) audio output interface: sdout - serial audio output port data output audio data serial output pin. this is also a start-up option pin, and requires a pull-up or pull-down resistor. osclk - serial audio output port bit clock input or output serial bit clock for audio data on the sdout pin.
66 ds245f4 cs8420 olrck - serial audio output port left/right clock input or output word rate clock for the audio data on the sdout pin. the fr equency will be at the output sample rate (fso). aes3/spdif transmitter interface: txn, txp - differential line driver outputs differential line driver output s, transmitting aes3 type data. drivers are pulled to low wh ile the cs8420 is in the reset state. tcbl - transmit channel status block start when operated as output, tcbl is high during the first su b-frame of a transmitted channel status block, and low at all other times. when o perated as input, driving tcbl high for at least three omck clocks will cause the current transmitted sub-frame to be the start of a channel status block. aes3/spdif receiver interface: rxp, rxn - differential line receiver inputs differential line rece iver inputs, carryi ng aes3 type data. rmck - input section recovered master clock output input section recovered master clock output. will be at a freq uency of 256x the i nput sample rate (fsi). this is also a start-up option pin, and requires a pull-up or pull-down resistor. rerr - receiver error indicator output when high, indicates a problem with the operation of the aes3 receiver. the status of this pin is updated once per sub-frame of incoming aes3 data. conditions that cause rerr to go high are: parity error, and bi-phase coding error, as well as loss of lock in the pll. this is also a start-up option pin, and requires a pull-up or pull-down resistor. emph /u - pre-emphasis indicator output or u-bit data input the emph /u pin either reflects the state of the emph channel status bits in the in coming aes3 type data stream, or is the serial u-bit input for th e aes3 type transmitted data , clocked by olrck. if indicating emphasis emph /u is low when the incoming data indicates 50/15 s pre-emphasis and high otherwise. copy - copy channel status bit output the copy pin reflects the state of the copy channel status bit in the incoming aes3 type data stream. this is also a start-up option pin, and requires a pull-up or pull-down resistor. orig - original channel status output scms generation indicator. this is decoded from the inco ming category code and the l bit. a low output indicates that the audio data stream is 1st generation or higher. a high indicates that the audio data stream is original. this is also a start-up option pin, and requires a pull-up or pull-down resistor. pro/c - professional channel status bit output or c-bit data input the pro/c pin either reflects the state of the professio nal/consumer channel status bi t in the incoming aes3 type data stream, or is the serial c-bit input for the aes3 type transmitted data, clocked by olrck. audio /v - audio channel status bit output or v-bit data input the audio /v pin either reflects the state of the audio/non audio chan nel status bit in the incoming aes3 type data stream, or is the v-bit data in put for the aes3 type transmitted data stream, clocked by olrck.
ds245f4 67 cs8420 13.5 hardware mode 4 description (transceive data flow, no src) hardware mode 4 data flow is shown in figure 27 . audio data is input via the aes3 receiver, and routed to the serial audio output port. different audio data synchronous to rmck may be input into the serial audio input port, and output via the aes3 transmitter. the channel status data, user data, and validity bit information are handled in two alternative modes: 4a and 4b, determined by a start-up resistor on the copy pin. in mode 4a, the received pro, copy, orig, emph , and audio channel status bits are output on pins. th e transmitted channel st atus bits are copied from the received channel status data, and the transmitted u and v bits are 0. in mode 4b, only the copy and orig pins are output, and reflect the received channel status data. the transmitted channel status bits, user data, and va lidity bits are input seri ally via the pro/c, emph /u, and audio /v pins. figure 20 shows the timing requirements. the apms pin allows the serial audio input port to be set to master or slave. if a validity, parity, bi-phase, or lock receiver error occurs, the current audio sample is passed unmodified to the serial audio output port. start-up options are shown in table 13 , and allow choice of the serial audio output port as a master or slave, whether tcbl is an input or an outp ut, the audio serial ports formats, and the source of the transmitted c, u, and v data. the following pages contain the detailed pin descriptions for hardware mode 4. aes3 encoder &tx serial audio output aes3 rx & decoder c&ubitdatabuffer rxp rxn olrck osclk sdout txp txn rmck rerr copy orig emph/u audio/v tcbl dfc0 dfc1 vd+ h/s power supply pins (vd+, va+, dgnd, agnd) & the reset pin (rst) and the pll filter pin (filt) are omitted from this diagram. please refer to the typical connection diagram for hook-up details. vd+ serial audio input ilrck isclk sdin pro/c apm s figure 27. hardware mode 4 - transceive data flow, without src
68 ds245f4 cs8420 sdout rmck rerr orig copy function lo - - - - serial output port is slave hi - - - - serial output port is master - - - - lo mode 4a: c transmitted data is copied from received data, u & v =0, received pro, emph , audio is visible - - - - hi mode 4b: cuv transmitted data is input serially on pins, received pro, emph and audio is not visible - lo lo - - serial input & output format if1&of1 - lo hi - - serial input & output format if2&of2 - hi lo - - serial input & output format if3&of3 - hi hi - - serial input & output format if1&of5 - - - lo - tcbl is an input - - - hi - tcbl is an output table 13. hardware mode 4 start-up options
ds245f4 69 cs8420 13.5.1 pin description - hardware mode 4 overall device control: dfc0, dfc1 - data flow control inputs dfc0 and dfc1 inputs determine th e major data flow options available in hardware mode, according to table 5 . audio input interface: sdin - serial audio input port data input audio data serial input pi n. this data will be trans mitted out the aes3 port. isclk - serial audio input port bit clock input or output serial bit clock for audio data on the sdin pin. ilrck - serial audio input port left/right clock input or output word rate clock for the audio data on the sdin pin. the frequency will be at the input sample rate (fsi) apms - serial audio input port master or slave apms should be connected to vd+ to set serial audio inpu t port as a master, or con nected to dgnd to set the port as a slave. audio output interface: sdout - serial audio output port data output audio data serial output pin. this is also a start-up option pin, and requires a pull-up or pull-down resistor.
70 ds245f4 cs8420 osclk - serial audio output port bit clock input or output serial bit clock for audio data on the sdout pin. olrck - serial audio output port left/right clock input or output word rate clock for the audio data on the sdout pin. the fr equency will be at the in put sample rate (fsi). aes3/spdif transmitter interface: txn, txp - differential line driver outputs differential line driver output s, transmitting aes3 type data. drivers are pulled to low wh ile the cs8420 is in the reset state. tcbl - transmit channel status block start when operated as output, tcbl is high during the first su b-frame of a transmitted channel status block, and low at all other times. when operat ed as input, driving tcbl high for at leas t three rmck clocks will cause the current transmitted sub-frame to be the start of a channel status block. aes3/spdif receiver interface: rxp, rxn - differential line receiver inputs differential line rece iver inputs, carryi ng aes3 type data. rmck - input section recovered master clock output input section recovered master clock output. will be at a freq uency of 256x the i nput sample rate (fsi). this is also a start-up option pin, and requires a pull-up or pull-down resistor. rerr - receiver error indicator output when high, indicates a problem with the operation of the aes3 receiver. the status of this pin is updated once per sub-frame of incoming aes3 data. conditions that cause rerr to go high are: parity error, and bi-phase coding error, as well as loss of lock in the pll. this is also a start-up option pin, and requires a pull-up or pull-down resistor. emph /u - pre-emphasis indicator output or u-bit data input the emph /u pin either reflects the state of the emph channel status bit in the in coming aes3 type data stream, or is the serial u-bit input for the aes3 type transmitted data, clocked by olrck. if indicating emphasis emph /u is high when the incoming data indicates 50/15 s pre-emphasis and low otherwise. copy - copy channel status bit output the copy pin reflects the state of the copy channel status bit in the incoming aes3 type data stream. this is also a start-up option pin, and requires a pull-up or pull-down resistor. orig - original channel status output scms generation indicator. this is decoded from the inco ming category code and the l bit. a low output indicates that the audio data stream is 1st generation or higher. a high indicates that the audio data stream is original. this is also a start-up option pin, and requires a pull-up or pull-down resistor. pro/c - professional channel status bit output or c-bit data input the pro/c pin either reflects the state of the professio nal/consumer channel status bi t in the incoming aes3 type data stream, or is the serial c-bit input for the aes3 type transmitted data, clocked by olrck. audio /v - audio channel status bit output or v-bit data input the audio /v pin either reflects the state of the audio/non audio chan nel status bit in the incoming aes3 type data stream, or is the v-bit data in put for the aes3 type transmitted data stream, clocked by olrck.
ds245f4 71 cs8420 13.6 hardware mode 5 description (aes3 receiver only) hardware mode 5 data flow is shown in figure 28 . audio data is input via the aes3 receiver, and routed to the serial audio output port. the pro, copy, orig, emph , and audio channel status bits are output on pins. the decoded c and u bits are also output, cloc ked by both edges of olrck (master mode only, see figure 19 ). if a validity, parity, bi-phase, or lock receiver error occurs, the current audio sample is passed unmodified to the serial audio output port. start-up options are shown in table 14 , and allow choice of the serial audio output port as a master or slave, and the serial audio port format. the following pages contain the detailed pin descriptions for hardware mode 5. sdout orig emph function lo - - serial output port is slave hi - - serial output port is master - lo lo serial output format of1 - lo hi serial output format of2 - hi lo serial output format of3 - hi hi serial output format of5 table 14. hardware mode 5 start-up options serial audio output aes3 rx & decoder c&ubitdatabuffer rxp rxn olrck osclk sdou t rmck rerr copy orig emph rcbl pro audio chs dfc0 dfc1 s/aes vd+ h/s power supply pins (vd+, va+, dgnd, agnd) & the reset pin (rst) and the pll filter pin (filt) are omitted from this diagram. please refer to the typical connection diagram for hook-up details. vd+ vd+ nverr c u omck figure 28. hardware mode 5 - aes3 receiver only
72 ds245f4 cs8420 13.6.1 pin description - hardware mode 5 overall device control: dfc0, dfc1 - data flow control inputs dfc0 and dfc1 inputs determine the major data flow options available in hardware mode, according to ta b l e 5 . s/aes - serial audio or aes3 input select s/aes is connected to dgnd in hardware mode 5, in order to select the aes3 input. omck - output section master clock input output section master clo ck input. this pin is not used in this mode and should be connected to dgnd. audio output interface: sdout - serial audio output port data output audio data serial output pin. this is also a start-up option pin, and requires a pull-up or pull-down resistor. osclk - serial audio output port bit clock input or output serial bit clock for audio data on the sdout pin. olrck - serial audio output port left/right clock input or output word rate clock for the audio data on the sdout pin. the fr equency will be at the in put sample rate (fsi).
ds245f4 73 cs8420 aes3/spdif receiver interface: rxp, rxn - differential line receiver inputs differential line receiver i nputs, carrying aes3 type data. rmck - input section reco vered master clock output input section recovere d master clock output . will be at a frequency of 256x the input sample rate (fsi). rerr - receiver error indicator when high, indicates a proble m with the operation of the aes3 receiver. the status of this pin is updated once per sub-frame of incoming aes3 data. conditions that cause rerr to go high are: validity, parity error, and bi-phase coding error, as well as loss of lock in the pll. nverr - no validity receiver error indicator when high, indicates a proble m with the operation of the aes3 receiver. the status of this pin is updated once per frame of incoming aes3 data. conditions t hat cause nverr to go high are: pari ty error, and bi-p hase coding error, as well as loss of lock in the pll. emph - pre-emphasis indicator output emph is low when the inco ming aes3 data indicates the presence of 50/15 s pre-emphasis. when the aes3 data indicates the absence of pre-emphasis or the presence of non 50/15 s pre-emphasis emph is high. this is also a start-up option pin, and requires a pull-up or pull-down resistor. copy - copy channel status bit output the copy pin reflects the state of the copy channel status bit in the incoming aes3 type data stream. orig - original channel status output scms generation indicator. this is decoded from the incoming category code and the l bit. a low output indicates that the audio data stream is 1st generation or higher. a hi gh indicates that the audio data stream is original. this is also a start-up option pin, and requires a pull-up or pull-down resistor. pro - professional channel status bit output the pro pin reflects the state of th e professional/consumer channel status bit in the incoming aes3 type data stream. audio - audio channel status bit output the audio pin reflects the st ate of the audio/non audio ch annel status bit in the inco ming aes3 type data stream. rcbl - receiver channel status block output rcbl indicates the beginning of a received channel status block. rcbl goes high 2 fram es after the reception of a z preamble, remains high for 16 fr ames while copy, orig, audio, emph and pro are updated, and returns low for the remainder of the block. rcbl changes on rising edges of rmck. chs - channel select input selects which sub-frame?s channel st atus data is output on the emph , copy, orig, pro and audio pins. chan- nel a is selected when chs is low, ch annel b is selected when chs is high. u - user data output the u pin outputs user da ta from the aes3 re ceiver, clocked by rising and falling edges of olrck. c - channel status data output the c pin outputs cha nnel status data from the aes3 receiver, clocked by rising and falling edges of olrck.
74 ds245f4 cs8420 13.7 hardware mode 6 description (aes3 transmitter only) hardware mode 6 data flow is shown in figure 29 . audio data is input via the serial audio input port and routed to the aes3 transmitter. the transmitted channel status, user, and validity data may be input in two alternative methods, determined by the state of the cen pin. mode 6a is selected when the cen pin is low. in mode 6a, the user data and validity bit are input via the u and v pins, clocked by both edges of ilrck. the c hannel status data is de- rived from the state of the copy/c, orig, emph , and audio pins. table 15 shows how the copy/c and orig pins map to channel status bits. in consumer mode, the transmitted category code shall be set to sample rate converter (0101100b). mode 6b is selected when the cen pin is high. in mode 6b, the channel status, user data and validity bit are input serially via the copy/c, u, and v pins. these pins are clocked by both edges of ilrck (if the port is in master mode). figure 20 shows the timing requirements. the channel status block pin (tcbl) may be an input or an output, determined by the state of the tcbld pin. the serial audio input port data format is selected as shown in ta b l e 1 5 , and may be set to master or slave by the state of the apms input pin. the following pages contain detailed pin descriptions for hardware mode 6. aes3 encoder &tx serial audio input c, u, v data buffer ilrck isclk txp copy/c orig emph audio tcbl dfc0 dfc1 s/aes vd+ h/s output clock source omck power supply pins (vd+, va+, dgnd, agnd) & the reset pin (rst) are omitted from this dia g ram. please refer to the t y pical connection dia g ram for hook-up details. vd+ sdin sfmt1 sfmt0 vd+ filt txn ce n u v vd+ tcbld apms figure 29. hardware mode 6 - aes3 transmitter only
ds245f4 75 cs8420 table 16. hw 6 serial port format selection copy/c orig function 00 pro=0, copy=0, l=0 01 pro=0, copy=0, l=1 10 pro=0, copy=1, l=0 11 pro=1 table 15. hw 6 copy/c and orig pin function sfmt1 sfmt0 function 00 serial input format if1 01 serial input format if2 10 serial input format if3 11 serial input format if4
76 ds245f4 cs8420 13.7.1 pin description - hardware mode 6 overall device control: dfc0, dfc1 - data flow control inputs dfc0 and dfc1 inputs determine the major data flow options available in hardware mode, according to ta b l e 5 . s/aes - serial audio or aes3 input select s/aes is connected to vd+ in hard ware mode 6, in order to select the serial audio input. sfmt0, sfmt1 - serial audio input port data format select inputs sfmt0 and sfmt1 select the serial audio input port format. see ta b l e 1 5 . omck - output section master clock input output section master clock inpu t. the frequency must be 256x the output sample rate (fso). audio input interface: sdin - serial audio input port data input audio data serial input pin. isclk - serial audio input port bit clock input or output serial bit clock for audio data on the sdin pin. *pinswhich r emain the same function in all modes . copy/c dfc0 emph sfmt0 sfmt1 va+ agnd filt rst apms tcbld ilrck isclk sdin 28 27 26 25 *24 *23 *22 21 20 19 18 17 16 15 1 2 3 4 5 6* 7* 8* 9* 10 11 12 13 14 orig dfc1 txp txn h/s vd+ dgnd omck s/aes audio u v cen tcbl
ds245f4 77 cs8420 ilrck - serial audio input port left/right clock input or output word ra te clock for the audio data on the sdin pin. apms - serial audio input port master or slave. apms should be connected to vd+ to set serial audio input port as a master, or connected to dgnd to set the port as a slave. aes3/spdif transmitter interface: txn, txp - differential line driver outputs differential line driver outputs, transmitting aes3 type data. drivers are pulled to low while the cs8420 is in the reset state. tcbl - transmit channel status block start when operated as output, tcbl is high during the first s ub-frame of a transmitted channel status block, and low at all other times. when opera ted as input, driving tcbl high for at least three omck clocks will cause the current transmitted sub-frame to be the st art of a channel status block. tcbld - transmit channel status block direction input connect tcbld to vd+ to set tcbl as an output. connect tcbld to dgnd to set tcbl as an input. emph - pre-emphasis indicator input in mode 6b, emph pin low sets the 3 emph channel status bits to indicate 50/15 s pre-emphasis. if emph is high the 3 emph channel status bits are set to 000 indicating no pre-emphasis. copy/c - copy channel status bit input or c bit input in mode 6b, the copy/c pin determines the state of t he copy, pro and l channel status bits in the outgoing aes3 type data stream (see table 15 ). in mode 6a, the copy/c pin become s the direct c bit input data pin. orig - orig channel status bit input in mode 6b, the orig pin de termines the state of the co py, pro and l channel status bits in the outgoing aes3 type data stream. see ta b l e 1 5 . audio - audio channel status bit input in mode 6b, the audio pin determines the st ate of the audio/non audio channe l status bit in the outgoing aes3 type data stream. v - validity bit input in modes 6a and 6b, the v pin input determines the state of the validity bit in the outgoing aes3 transmitted data. this pin is sampled on both edges of the ilrck. u - user data bit input in modes 6a and 6b, the u pin input determines the state of the user data bit in the outgoing aes3 transmitted data. this pin is sampled on both edges of the ilrck. cen - c bit input en able mode input the cen pin determines how the channel status data bits are input. when ce n is low, hardware mode 6a is se- lected, where the copy/c, orig, emph and audio pins are used to enter selected channel status data. when cen is high, hardware mode 6b is se lected, where the copy/c pin is used to enter serial channel status data.
78 ds245f4 cs8420 14. external aes3/spdif/iec609 58 transmitter and receiver components this section details th e external comp onents required to interface the aes3 tr ansmitter and receiver to cables and fiber-optic components. 14.1 aes3 transmitter external components the output drivers on the cs8420 are designed to driv e both the professional and consumer interfaces. the aes3 specification for professional/b roadcast use calls for a 110 source impedance and a balanced drive capability. since the tran smitter output impedance is very low, a 110 resistor should be placed in series with one of the transmit pins. the specifications call for a balanced output drive of 2-7 volts peak-to-peak into a 110 load with no cable attached. using the circuit in figure 30 , the output of the transformer is short- circuit protected, has the proper source impedance, and provides a 5 volts peak-to-peak signal into a 110 load. lastly, the two output pins should be attached to an xlr connector with male pins and a female shell, and with pin 1 of the connector grounded. in the case of consumer use, the iec60958 specific ations call for an unbalanced drive circuit with an output impedance of 75 and a output drive level of 0.5 v peak-to-peak 20% when measured across a 75 load using no cable. the circuit shown in figure 31 only uses the txp pin and prov ides the proper output imped- ance and drive level using standard 1% resistors. the connector for a consumer application would be an rca phono socket. this circuit is also short circuit protected. 110-(r txp +r txn ) txp txn xlr 1 cs8420 figure 30. professional output circuit 374-r txp 90.9 txp txn rca phono cs8420 figure 31. consumer output circuit
ds245f4 79 cs8420 the txp pin may be used to drive ttl or cmos gates as shown in figure 32 . this circuit may be used for optical connectors for digital audio since they usually have ttl or cmos compatible inputs. this circuit is also useful when driving multiple digital audio output s since rs422 line drivers ha ve ttl compatible inputs. 14.2 aes3 receiver ex ternal components the cs8420 aes3 receiver is designed to accept both the professional and cons umer interfaces. the dig- ital audio specifications for professional use call fo r a balanced receiver, using xlr connectors, with 110 20% impedance. the xlr connector on the receiver shoul d have female pins with a male shell. since the receiver has a very high input impedance, a 110 resistor should be placed across the receiver terminals to match the line impedance, as shown in figure 33 . although transformers are not required by the aes, they are, however, strongly recommended. if some isolation is desired witho ut the use of transformers, a 0.01 f capacitor should be placed in series with each input pin (rxp and rxn) as shown in figure 34 . however, if a transformer is not used, high frequency energy could be coupled into the receiv er, causing degradation in analog performance. figures 33 and 34 show an optional dc blocking capacitor (0.1 f to 0.47 f) in series with the cable input. this improves the robustness of the receiver, preventin g the saturation of the transformer, or any dc current flow, if a dc voltage is present on the cable. in the configuration of systems, it is important to avoid ground loops and dc current flowing down the shield of the cable that could result when boxes with diffe rent ground potentials are connected. generally, it is good practice to ground the shield to the chassis of the transmitting unit, and connect the shield through a capacitor to chassis ground at the receiver. however, in some cases it is advantageous to have the ground of two boxes held to the same potential, and the cable shield might be depended upon to make that electrical txp txn ttl or cmos gate cs8420 figure 32. ttl/cmos output circuit 1 xlr twisted pair 110 110 cs8420 rxp rxn *seetext figure 33. professional input circuit 1 xlr twisted pair 110 110 cs8420 rxp rxn 0.01 f 0.01 f *seetext figure 34. transformerless professional input circuit
80 ds245f4 cs8420 connection. generally, it may be a good idea to provid e the option of grounding or capacitively coupling the shield to the chassis. in the case of the consumer interface, the standards call for an unbalanced circuit having a receiver imped- ance of 75 5%. the connector for the c onsumer interface is an rca phono socket. the receiver circuit for the consumer interface is shown in figure 35 . the circuit shown in figure 36 may be used when external rs422 receivers, optical receivers or other ttl/cmos logic outputs drive the cs8420 receiver section. 14.3 isolating transformer requirements the transformer should be capable of operating from 1.5 to 14 mhz, which is equivalent to an audio data rate of 25 khz to 108 khz after bi-phase mark encoding. transformers provide isolation from ground loops, 60 hz noise, and common mode noise and interference . one of the important considerations when choos- ing transformers is minimizing sh unt capacitance between primary and secondary windings. the higher the shunt capacitance, the lower the is olation between primary and secondary, and the more coupling of high frequency energy. this energy appears in the form of common mode noise on the receive side ground and has the potential to degrade analog performance. th erefore, for best performance, shielded transformers optimized for minimum shunt capacitance should be used. see application note 134 for a selection of man- ufacturers and their part numbers. rca phono rxp rxn cs8420 coax 75 75 0.01 f 0.01 f figure 35. consumer input circuit rxp rxn cs8420 0.01 f 0.01 f ttl/cmos gate figure 36. ttl/cmos input circuit
ds245f4 81 cs8420 15. channel status and user data buffer management the cs8420 has a comprehensive channel status (c) and us er (u) data buffering scheme, which allows automatic management of channel status bl ocks and user data. alternatively, sufficient control and access is provided to allow the user to completely manage the c and u data via the control port. 15.1 aes3 channel status(c) bit management the cs8420 contains sufficient ram to store a full blo ck of c data for both a and b channels (192x2 = 384 bits), and also 384 bits of u information. the user may read from or write to thes e rams via the control port. unlike the audio data, it is not possible to 'sample-ra te' convert the c bits. this is because specific meanings are associated with fixed-length data patterns, which s hould not be altered. since the output data rate of the cs8420 will differ from the input rate w hen sample-rate conversion is done, it is not feas ible to directly trans- fer incoming c data to the output. the cs8420 manages the flow of channel status data at the block level, meaning that entire blocks of channel status information are buffered at the input, synchronized to the output timebase, and then transmitted. the buffering schem e involves a cascade of three block-sized buffers, named d,e, and f as shown in figure 37 . the msb of each byte represents the first bit in the serial c data stream. for example, the msb of byte 0 (which is at control port address 20h) is the consumer/professional bit for channel status block a. the first buffer, d, accept s incoming c data from the aes receiver. the 2nd buffer, e, accepts entire blocks of data from the d buffer. the e buffer is also accessib le from the control port, a llowing read and writing of the c data. the 3rd buffer (f ) is used as the source of c data for the aes3 transm itter. the f buffer accepts block transfers from the e buffer. if the input rate is slower than t he output rate (so that in a given time interval, more channel status blocks are transmitted than received), some buffered c blocks will be transmitted multiple times. if the input rate is faster than the ou tput rate, some will not be transmitted at all. th is is illustrated in ( figure 38 ). in this manner, channel status block integrity is maintained. if the tr ansmitted sample count bits are important in the appli- cation, then they will need to be updated via the control port by th e microcontroller for every outgoing block. control port from aes3 receiver to aes3 transmitte r e 24 words 8-bits 8-bits ab df received data buffer transmit data buffer figure 37. channel status data buffer structure
82 ds245f4 cs8420 15.1.1 manually accessing the e buffer the user can monitor the data being transferred by re ading the e buffer, which is mapped into the register space of the cs8420, via the contro l port. the user can modify the data to be transmitted by writing to the e buffer. the user can configure the interrupt enable register to cause interrupts to occur whenever d-to-e or e-to- f buffer transfers occur. this allows determination of the allowable time periods to interact with the e buff- er. also provided are d-to-e and e-to-f inhibit bits. th e associated buffer transfer is disabled whenever the user sets these bits. these may be used whenever ?long ? control port interactions are occurring. they can also be used to align the behavior of the buffers with the selected audio data flow. for example, if the audio data flow is serial po rt in to aes3 out, then it is necessary to inhibit d-to-e tr ansfers, since these would overwrite the desired transmit c data with invalid data. flowcharts for reading and writing to the e buffer are shown in figures 39 and 40 . for reading, since a d- to-e interrupt just o ccurred, then there a substantial time interv al until the next d-to-e transfer (approxi- mately 192 frames worth of time). this is usually pl enty of time to access the e data without having to inhibit the next transfer. for writing, the sequence starts after a e-to-f transfer, which is based on the out- put timebase. since a d-to-e transfer could occur at any time (this is based on the input timebase), then it is important to inhibit d-to-e tr ansfers while writing to the e buffer un til all writes are complete. then wait until the next e-to-f trans fer occurs before enabling d-to-e transfers. this ensu res that the data written to the e buffer actually gets transmitted and not overwritten by a d-to-e transfer. if the channel status block to transmit indicates pr o mode, then the crcc byte is automatically calcu- lated by the cs8420, and does not have to be written in to the last byte of the bl ock by the host microcon- troller. block 1 block 2 block 3 block 4 block 5 block 1 block 1 block 2 block 3 block 3 block 4 block 5 contents of e buffer updated at fsi rate contents of f buffer updated from e output at fso rate fso > fsi (3/2) causes blocks 1 and 3 to be transmitted twice fso < fsi (2/3) causes blocks 3 and 6 to not be transmitted contents of e buffer updated at fsi rate contents of f buffer updated from e output at fso rate block 1 block 2 block 3 block 4 block 5 block 6 block 7 block 1 block 2 block 4 block 5 block 7 figure 38. channel status block handling when fso is not equal to fsi d to e interrupt occurs optionally set d to e inhibit read e data if set, clear d to e inhibit r e t u rn figure 39. flowchart for reading the e buffer
ds245f4 83 cs8420 . 15.1.2 reserving the first 5 bytes in the e buffer d-to-e buffer transfers periodically overwrite the data stored in the e buffer. this can be a problem for users who want to transmit certain channel status se ttings which are different from the incoming settings. in this case, the user would have to superimpose his se ttings on the e buffer after every d-to-e overwrite. to avoid this problem, the cs8420 ha s the capability of reserving the fi rst 5 bytes of the e buffer for user writes only. when this capability is in use, internal d-to-e buffer transfers will not affect the first 5 bytes of the e buffer. therefore, the user can set values in these first 5 e bytes once, and the settings will persist until the next user change. this mode is enabled vi a the channel status data buffer control register. 15.1.3 serial copy mana gement system (scms) in software mode, the cs8420 allows read/modify/write access to all the channel status bits. for con- sumer mode scms compliance, the host microcontro ller needs to read and manipulate the category code, copy bit and l bit appropriately. in hardware mode, the scms protocol can be followed by either using the copy and orig input pins, or by using the c bit serial input pin. these options are documented in the hardware mode section of this data sheet (see ?hardware modes? on page 55 ) 15.1.4 channel status data e buffer access the e buffer is organized as 24 x 16-bit words. for each word the ms byte is the a channel data, and the ls byte is the b channel data (see figure 37 ). there are two methods of accessing this memory, known as one-byte mode and two-byte mode. the de- sired mode is selected via a control register bit. e to fi nterrupt occurs optionally set e to f inhibit clear d to e inhibit if set, clear e to f inhibit r e t u rn set d to e inhibit write e data wait for e to f transfer figure 40. flowchart for writing the e buffer
84 ds245f4 cs8420 15.1.5 one-byte mode in many applications, the channel status blocks for the a and b chan nels will be identical. in this situation, if the user reads a byte from one of the channel's bl ocks, the corresponding byte for the other channel will be the same. similarly, if the user wrote a byte to one channel's block, it would be necessary to write the same byte to the other block. one-byte mode take s advantage of the often id entical nature of a and b channel status data. when reading data in one-byte mode, a single byte is returned, which can be from channel a or b data, depending on a register control bit. if a write is being done, the cs8420 expects a single byte to be input to its control port. this byte will be written to both the a a nd b locations in the addressed word. one-byte mode saves the user subs tantial control port access time, as it effectively accesses 2 bytes? worth of information in 1 byte's worth of access ti me. if the control port's auto-increment addressing is used in combination with this mode, multi-byte accesses such as full-block reads or writes can be done especially efficiently. 15.1.6 two-byte mode there are those applicat ions in which the a and b channel status blocks will not be the same, and the user is interested in accessing both blocks. in thes e situations, two-byte mode should be used to access the e buffer. in this mode, a read will cause the cs8420 to output two bytes from its control port. the first byte out will represent the a channel stat us data, and the 2nd byte will represent the b channel status data. writing is similar, in that two bytes must now be input to the cs8420's control port. the a channel status data is first, b channel status data second. 15.2 aes3 user (u) bit management the cs8420 u bit manager has four operating modes: mode 1. transmit all zeros mode 2. block mode mode 3. reserved mode 4. iec consumer b 15.2.1 mode 1: transmit all zeros mode 1 causes only zeros to be transmitted in the output u data, regardless of e buffer contents or u data embedded in an input aes3 data str eam. this mode is inte nded for the user who do es not want to trans- ceive u data, and simply wants the ou tput u channel to contain no data. 15.2.2 mode 2: block mode mode 2 is very similar to the scheme used to control the c bits. entire blocks of u data are buffered from input to output, using a cascade of three block-sized rams to perform the buffering. the user has access to the second of these three buffers, denoted the e bu ffer, via the control port. block mode is designed for use in aes3 in, aes3 out situatio ns in which input u data is decod ed using a microcon troller via the control port. it is also the only mode in which the user can merge his/her own u data into the transmitted aes3 data stream. the u buffer access only operates in two-byte mode, since there is no concept of a and b blocks for user data. the arrangement of the data in the each byte is th at the msb is the first received bit and is the first
ds245f4 85 cs8420 transmitted bit. the first byte read is the first byte received, and the firs t byte sent is the first byte trans- mitted. 15.2.3 iec60958 recommended u data fo rmat for consumer applications modes (3) and (4) are inten ded for use in aes3 in, aes3 out situatio ns, in which the input u data is for- matted as recommended in the ?iec60958 digital audio interface, part 3: consumer applications? docu- ment. in this format, ?messages? are formed in the u data from information units or ius. an iu is 8 bits long, and the msb is always 1, and is called the start bit, or 'p' bit. the remaining 7-bits ar e called q, r, s, t, u, v, & w, and carry the desired data. a ?message? consists of 3 to 129 ius. multiple ius ar e considered to be in the same message if they are separated by 0 to 8 zeros, denoted her e as filler. a filler sequence of ni ne or more zeros indicates an inter- message gap. the desired information is normally carr ied in the sequence of corresponding bits in the ius. for example, the sequential q bits from each iu make up the q sub-code data that is used to indicate compact disk track informatio n. this data is automatically extracte d from the received iec60958 stream, and is presented in the control port register map space. where incoming u data is coded in the above format, and needs to be re-trans mitted, the data transfer cannot be done using shift registers, because of th e different fsi and fso sampling clocks. instead, input data must be buffered in a fifo structure, and then read out by th e aes3 transmitter at appropriate times. each bit of each iu must be transceived; unlike the audio samples, there can be no sample rate conver- sion of the u data. therefore, there are two potential problems: (1) message partitioning when fso > fsi, more data is tr ansmitted than received per unit ti me. the fifo will fr equently be com- pletely emptied. sensible behavior must occur when th e fifo is empty, otherwise, a single incoming mes- sage may be erroneously partition ed into multiple, smaller, messages. (2) overwriting when fso < fsi, more data is received than transmit ted per unit time. there is a danger of the fifo be- coming completely full, a llowing incoming data to overwrite data that has not yet been output through the aes3 transmitter. 15.2.4 mode (3): reserved this mode has been removed. use iec consumer mode b. 15.2.5 mode (4): iec consumer b in this mode, the partitioning problem is solved by buffering an entire message before starting to transmit it. in this scheme, zero-segments between messages will be expanded when fso > fs i, but the integrity of individual mess ages is preserved. the overwriting problem (when fso < fs i) is solved by only storing a po rtion of the input u data in the fifo. specifically, only the ius them selves are stored (and not the zeros that provide inter-iu and inter- message ?filler?). an in ter-iu filler segment of fixe d length (of) will be added back to the messages at the fifo output, where the length of of is equal to the shortest ob served input fille r segment (if). storing only ius (and not filler) with in the fifo makes it possible for the slower aes3 transmitter to ?catch up? to the faster aes3 receiver as da ta is read out of the fifo. this is because nothing is written into the fifo when long strings of zeros are input to the a es-ebu receiver. during this time of no writing, the
86 ds245f4 cs8420 transmitter can read out data that had previously accu mulated, allowing the fifo to empty out. if the fifo becomes completely empty, zeros are transmitted unt il a complete message is written into the fifo. mode 4 is not fail-safe; the fifo ca n still get completely full if there isn't enough ?zero- padding? between incoming messages. it is up to the user to provide proper padding, as defined below: minimum padding = (fsi/fso - 1)*[8n + (n-1)*if +9] + 9 where n is the number of ius in the message, if is the number of filler bits between each iu, and fso fsi. example 1: fsi/fso = 2, n=4, if=1: minimum proper padding is 53 bits. example 2: fsi/fso = 1, n=4, if=7 : min proper padding is 9 bits. the cs8420 detects when an overwrite has occurred in the fifo, and synchronously resets the entire fifo structure to preven t corrupted u data from be ing merged into the tran smitted aes3 data stream. the cs8420 can be configured to generate an interrupt when this occurs. mode 4 is recommended for properly formatted u data where mode 3 cannot provide acceptable perfor- mance, either because of a too-extr eme fsi/fso ratio, or because it's unacceptable to change the lengths of filler segments. mode 4 provides error-free perfo rmance over the complete ra nge of fsi/fso ratios (pro- vided that the input messages are properly zero-padded for fsi > fso).
ds245f4 87 cs8420 16. pll filter 16.1 general an on-chip phase locked loop (pll) is used to recover the clock from the incoming data stream. figure 41 is a simplified diagram of the pll in cs8420 devices. when the pll is locked to an aes3 input stream, it is updated at each preamble in the aes3 stre am. this occurs at twic e the sampling frequency, f s . when the pll is locked to ilrck, it is updated at f s so that the duty cycle of the input doesn?t affect jitter. there are some applications where low jitter in the re covered clock, presented on the rmck pin, is impor- tant. for this reason, the pll has been designed to ha ve good jitter attenuation characteristics, as shown in figure 44 and figure 45 . in addition, the pll has been designe d to use only the preambles of the aes3 stream to provide lock update information to the pll. this results in the pll being immune to data-depen- dent jitter effects because the aes3 prea mbles do not vary with the data. the pll has the ability to lock onto a wide range of input samp le rates with no exte rnal compo nent changes. if the sample rate of th e input subsequently change s, for example in a varispeed application, the pll will only track up to 12.5% from the nominal center sample rate. the nominal center sample rate is the sample rate that the pll fi rst locks onto upon applicat ion of an aes3 data stream or after enabling the cs8420 clocks by setting the run control bit. if the 12.5% samp le rate limit is exceeded, the pll will return to its wide lock range mode and re-acquire a new nominal center sample rate. 16.2 external filter components 16.2.1 general the pll behavior is affected by the external filter component values. figure 5 on page 12 shows the rec- ommended configuration of the tw o capacitors and one resistor th at comprise the pll filter. in table 19 and table 20 , the component values shown for the 32 to 96 khz range have the highest corner frequency jitter attenuation curve, takes the shortest time to lo ck, and offers the best outp ut jitter performance. the component values shown in table 18 and table 20 for the 8to96khz range a llows the lowest input sam- ple rate to be 8 khz, and increases the lock time of th e pll. lock times are worst case for an fsi transition of 96 khz. phase comparator and charge pump n vco rmck input c rip c filt r filt figure 41. pll block diagram
88 ds245f4 cs8420 16.2.2 capacitor selection the type of capacitors used for the pll filter can have a significant effect on receiver performance. large or exotic film capacitors are not nec essary as their leads and the required longer circuit board traces add undesirable inductance to the circuit. surface mount ceramic capacitors are a good choice because their own inductance is low, and they can be mounted close to the filt pin to minimize trace inductance. for c rip , a c0g or npo dielectric is recommended, and for c filt , an x7r dielectric is preferred. avoid ca- pacitors with large temperature coefficients, or capacitors with high dielectric constants, that are sensitive to shock and vibration. these in clude the z5u and y5v dielectrics. 16.2.3 circuit board layout board layout and capacitor choice affect each ot her and determine the perfo rmance of the pll. figure 42 contains a suggested layout fo r the pll filter components and for bypassing the analog supply voltage. the 0.1 f bypass capacitor is in a 1206 form factor. r filt and the other three capacitors are in an 0805 form factor. the traces are on the top surface of the board with the ic so that there is no via inductance. the traces themselves are short to minimize the i nductance in the filter path. the va+ and agnd traces extend back to their origin and are shown only in truncated form in the drawing. 16.3 component value selection when transitioning from one revision of the part another, component values need to be changed. it is man- datory for customers to change the external pll component values when transitioning from revision d to revision d1. 16.3.1 identifying th e part revision the first line of the part marking on the package indicates the part number and package type cs8420-xx. table 17 shows a list of part revisions and thei r corresponding second line part marking, which indicates what revision the part is. table 17. second line part marking revision pre-october 2002 (10-digit) new (12-digit) d zxxxxxxxxx zfbadxxxxxxx d1 rxxxxxxxxx rfbad1xxxxxx va+ agnd filt c filt 1000 pf .1f r filt c rip figure 42. recommended layout example
ds245f4 89 cs8420 16.3.2 locking to the r xp/rxn receiver inputs cs8420 parts that are configured to lock to only the rxp/rxn receiver inputs should use the external pll component values listed in table 18 and table 19 . values listed for the 32 to 96 khz fs range will have the highest corner frequency jitter attenuation curv e, take the shortest time to lock, and offer the best output jitter performance. table 18. locking to rxp/rxn - fs = 8 to 96 khz table 19. locking to rxp/rxn - fs = 32 to 96 khz* * parts used in applicatio ns that are required to pass the aes3 or iec60958-4 specification for receiver jitter tolerance should use these component values. please note that the aes3 and iec60958 specifica- tions do not have allowances for locking to sample rates less than 32 khz or for locking to the ilrck input. also note that many factors can affect jitter perfor mance in a system. please fo llow the circuit and layout recommendations outlined previously. 16.3.3 locking to the ilrck input cs8420 parts that are configured to lock to the ilrck input should use the external pll component val- ues listed in table 20 . note that parts that need to lock to both ilrck and rxp/rxn should use these values. values listed for the 32 to 96 khz fs range will have the highest corner frequency jitter at- tenuation curve, take the shorte st time to lock, and offer th e best output jitter performance. table 20. locking to the ilrck input revision r filt (k )c filt ( f) c rip (nf) pll lock time (ms) d 0.909 1.8 33 56 d1 0.4 0.47 47 60 revision r filt (k )c filt ( f) c rip (nf) pll lock time (ms) d 3.0 0.047 2.2 35 d1 1.60.334.7 35 revision fs range (khz) r filt (k )c filt ( f) c rip (nf) pll lock time (ms) d 8 to 96 1.3 2.7 62 120 d 32-96 5.1 0.15 3.9 70 d1 8 to 96 0.3 1.0 100 120 d1 32-96 0.6 0.22 22 70
90 ds245f4 cs8420 16.3.4 jitter tolerance shown in figure 43 is the receiver jitter to lerance template as illustrated in the aes3 and iec60958-4 specification. cs8420 parts used with the appropri ate external pll component values (as noted in table 19 ) have been tested to pass this template. 16.3.5 jitter attenuation shown in figure 44 and figure 45 are jitter attenuation plots for the various revisions of the cs8420 when used with the appropriate external pll component values (as noted in table 19 ). the aes3 and iec60958-4 specifications do not have allowances for locking to sample rates less than 32 khz or for lock- ing to the ilrck input. these specif ications state a maximum of 2 db jitter gain or peaking. figure 43. jitter tolerance template 10 ?1 10 0 10 1 10 2 10 3 10 4 10 5 ?20 ?15 ?10 ?5 0 5 jitter frequency (hz) jitter attenuation (db) 10 ?1 10 0 10 1 10 2 10 3 10 4 10 5 ?25 ?20 ?15 ?10 ?5 0 5 jitter frequency (hz) jitter attenuation (db) figure 44. revision d jitter attenuation fig ure 45. revision d1 jitter attenuation
ds245f4 91 cs8420 17. parameter definitions input sample rate (fsi) the sample rate of the incoming digital audio. input frame rate the frame rate of the re ceived aes3 format data. output sample rate (fso) the sample rate of the outgoing digital audio. output frame rate the frame rate of the tran smitted aes3 format data. dynamic range the ratio of the maximum signal level to the noise floor. total harmonic distortion and noise the ratio of the noise and distortion to the test signal level. normally referenced to 0 dbfs. peak idle channel noise component with an all-zero input, what is the amplitude of th e largest frequency component visible with a 16k point fft. the value is in db ratio to full-scale. input jitter tolerance the amplitude of jitter on the aes3 st ream, or in the ilrck cl ock, that will cause measur able artifacts in the src output. test signal is full scale 9 khz, fsi is 48 kh z, fso is different 48 khz, jitter is 2 khz sinusoidal, and audio band white noise. aes3 transmitte r output jitter with a jitter free omck clock, what is the jitter added by the aes3 transmitter. gain error the difference in amplitude between the output and the input signal level, within the passband of the digital filter in the src.
92 ds245f4 cs8420 18. package dimensions thermal characteristics and specifications inches millimeters dim min max min max a 0.093 0.104 2.35 2.65 a1 0.004 0.012 0.10 0.30 b 0.013 0.020 0.33 0.51 c 0.009 0.013 0.23 0.32 d 0.697 0.713 17.70 18.10 e 0.291 0.299 7.40 7.60 e 0.040 0.060 1.02 1.52 h 0.394 0.419 10.00 10.65 l 0.016 0.050 0.40 1.27 0 8 0 8 parameter symbol min typ max units junction to ambient thermal impedance (28 pin soic) ja - 65 - c/w allowable junction temperature t j --135c 28l soic (300 mil bo dy) package drawing d h e b a1 a c l seating plane 1 e
ds245f4 93 cs8420 19. ordering information 20. revision history product description package pb-free grade temp range container order# cs8420 digital audio sample rate converter 28-soic no commercial -10o to +70oc rail CS8420-CS tape and reel CS8420-CSr yes commercial -10o to +70oc rail CS8420-CSz tape and reel CS8420-CSzr automotive -40o to +85oc rail cs8420-dsz tape and reel cs8420-dszr cdb8420 evaluation board for cs8420 - - - - - cdb8420 release changes pp1 1st preliminary release pp2 2nd preliminary release pp3 3rd preliminary release pp4 -added is package to front page. -added is package to ?ambient operating temperature:? on page 6 . -corrected ?minimizing group delay through multiple cs8420s when locking to ilrck? on page 28 . -revised ?src invalid state? on page 49 . pp5 -added ds package to front page. -added ds package to ?ambient operating temperature:? on page 6 . -corrected ?tdpd? on page 9 . -corrected ?tlmd? on page 9 . -corrected ?tsmd? on page 9 . -corrected ?tdh? on page 10 . -added ?c/u buffer data corruption? on page 49 pp6 -added lead-free ordering information. f1 final release 1 -changed format of figure 17 on page 20 and figure 18 on page 21 . -changed sores description to refer to sample rate converter as data source in ?serial audio output port data format (06h)? on page 39 . -added ?transmitter startup? on page 48 . -integrated d1 errata in section 16.2 on page 87 . f2 final release 2 -updated ordering information. -added ?block-mode u-data d-to-e buffer transfers? on page 50 . f3 final release 3 -updated ordering information. f4 final release 4 -updated leaded/lead-free information in ?ordering information? on page 93 .
94 ds245f4 cs8420 contacting cirrus logic support for all product questions and inquiries, c ontact a cirrus logic sales representative. to find the one nearest you, go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided "as is" without warran ty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual proper ty rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semic onductor products may involve potential risks of death, personal in jury, or severe prop- erty or environmental da mage ("critical applicatio ns"). cirrus products are not design ed, authorized or warranted for use in aircraft systems, military applications, products surgical ly implanted into th e body, automotive safe ty or security de- vices, life support products or other cri tical applications. inclus ion of cirrus products in s uch applications is under- stood to be fully at the customer's ri sk and cirrus disclaims and makes no wa rranty, express, statutory or implied, including the implied warra nties of merchantability and fitn ess for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or customer's customer uses or perm its the use of cirrus products in critical applications, customer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any and all liability, including attorneys' fe es and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. spi is a trademark of motorola inc. ac-3 is a registered trademark of dolby laboratories, inc. i2c is a registered trademark of philips semiconductor.

▲Up To Search▲

Price & Availability of CS8420-CS

	To Download CS8420-CS Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .